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KM416S1120D Scheda tecnica(PDF) 7 Page - List of Unclassifed Manufacturers |
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KM416S1120D Scheda tecnica(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 43 page KM416S1120D CMOS SDRAM - 7 - Rev. 1.4 (Jun. 1999) AC OPERATING TEST CONDITIONS (VDD = 3.3V ±0.3V*2, TA = 0 to 70°C) Parameter Value Unit Input levels (Vih/Vil) 2.4 / 0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr / tf = 1 / 1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 3.3V 1200 Ω 870 Ω Output VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Vtt=1.4V 50 Ω Output Z0=50 Ω (Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit 1. The DC/AC Test Output Load of KM416S1120D-C/6/7 is 30pF. 2. The VDD condition of KM416S1120D-C/6 is 3.135V~3.6V. Note : 50pF*2 50pF*1 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following clock unit based AC conversion table Notes : OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note -C -6 -7 -8 -10 CAS Latency CL 3 2 3 2 3 2 3 2 3 2 CLK CLK cycle time tCC(min) 5.5 - 6 - 7 8.7 8 10 10 12 ns Row active to row active delay tRRD(min) 2 CLK 1 RAS to CAS delay tRCD(min) 3 - 3 - 3 2 3 2 2 2 CLK 1 Row precharge time tRP(min) 3 - 3 - 3 2 3 2 2 2 CLK 1 Row active time tRAS(min) 7 - 7 - 7 5 6 5 5 4 CLK 1 tRAS(max) 100 us Row cycle time tRC(min) 10 - 10 - 10 7 9 7 7 6 CLK 1 Last data in to row precharge tRDL(min) 1 CLK 2, 5 Last data in to new col.address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK Mode Register Set cycle time tMRS(min) 2 CLK Number of valid output data CAS Latency=3 2 ea 4 CAS Latency=2 1 |
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