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ST16C2550IP40 Scheda tecnica(PDF) 5 Page - Exar Corporation

Il numero della parte ST16C2550IP40
Spiegazioni elettronici  DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFOS
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Produttore elettronici  EXAR [Exar Corporation]
Homepage  http://www.exar.com
Logo EXAR - Exar Corporation

ST16C2550IP40 Scheda tecnica(HTML) 5 Page - Exar Corporation

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ST16C2550
5
Rev. 3.20
SYMBOL DESCRIPTION
Symbol
Pin
Signal
Pin Description
40
44
48
type
individual channels, A through B. The state at these pin(s)
are defined by the user and through the software setting of
MCR register bit-3. INT A-B are set to the active mode and
OP2 to a logic 0 when MCR-3 is set to a logic 1. INT A-B are
set to the three state mode and OP2 to a logic 1 when MCR-
3 is set to a logic 0. See bit-3, Modem Control Register
(MCR bit-3).
RESET
35
39
36
I
Reset. (active high) - A logic 1 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time. (See ST16C2550 External Reset Conditions for ini-
tialization details.)
-RXRDY A-B
-
34,23 31,18
O
Receive Ready A-B (active low) - This function is associ-
ated with 44 pin PLCC and 48 pin TQFP packages only. This
function provides the RX FIFO/RHR status for individual
receive channels (A-B). RXRDY is primarily intended for
monitoring DMA mode 1 transfers for the receive data
FIFO’s. A logic 0 indicates there is receive data to read/
unload, i.e., receive ready status with one or more RX
characters available in the FIFO/RHR. This pin is a logic 1
when the FIFO/RHR is empty or when the programmed
trigger level has not been reached. This signal can also be
used for single mode transfers (DMA mode 0).
-TXRDY A-B
-
1,12
43,6
O
Transmit Ready A-B (active low) - This function is associ-
ated with 44 pin PLCC and 48 pin TQFP packages only.
These outputs provide the TX FIFO/THR status for indi-
vidual transmit channels (A-B). TXRDY is primarily in-
tended for monitoring DMA mode 1 transfers for the trans-
mit data FIFO’s. An individual channel’s -TXRDY A-B buffer
ready status is indicated by logic 0, i.e., at least one location
is empty and available in the FIFO or THR. This pin goes to
a logic 1 when there are no more empty locations in the
FIFO or THR. This signal can also be used for single mode
transfers (DMA mode 0).
VCC
40
44
42
Pwr
Power supply input.


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