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AD8475 Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD8475 Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 13 page Circuit Note CN-0385 Rev. 0 | Page 7 of 13 shorter conversion time, and it allows the user to return to acquisition phase before the end of conversion. Therefore, if the user runs the ADC at slower throughput, there is have more time to settle the kickback. The signal must be settled by the end of the acquisition phase for an accurate conversion. To maximize the time given for the signal to settle, the multiplexer switches channels immediately after the AD4003 begins its conversion phase. In addition to settling from the multiplexed signal from the output of the AD8475, the RC noise filter and AD4003 inputs also need to settle to the voltage kickback that occurs at the beginning of the acquisition phase. For more information, see the Analog Dialogue article, Front-End Amplifier and RC Filter Design for a Precision SAR Analog-to-Digital Converter. The settling time for the circuit in Figure 7 was simulated in NI Multisim, as shown in Figure 8. V1 represents the maximum voltage step expected at either input of the AD4003 (from a single-ended output of the AD8475). CNV and S1 simulate the AD4003 switching from the conversion phase (occurring when V1 changes value) to the acquisition phase (300 ns after start of conversion). CNV keeps S1 open until 300 ns after V1 steps from 0 V to 4 V to represent the transition from the conversion phase to the acquisition phase. ADC_IN is the voltage that is sampled by the AD4003 on a CNV rising edge. The settling time for this portion of the system is equal to the time between V1 switching to 4 V (at TIME = 0, see Figure 9) to ADC_IN settling to 0.001% of 4 V. Figure 8. Multisim™ Settling Time Model of the AD4003 and RC Noise Filter The simulation results are shown in Figure 9. The time taken for the output to settle to 0.001% of 4 V is tS_AD4003= 711 ns. Figure 9. Settling Time Waveforms for the AD4003 and RC Noise Filter Simulation Model Total System Settling Time The total settling time of the entire circuit shown in Figure 1 can now be estimated by calculating the rss of the settling times for each component: • tS_ADG5207 = 188 ns • tS_AD8251 = 1000 ns • tS_AD8475 = 200 ns • tS_AD4003 = 711 ns • ns 1257 ns 11 7 ns 200 μs 1 ns 188 t 2 2 2 2 S_TOTAL ≈ + + + = The expected maximum channel switching sample rate of the system is then kSPS 795 ns 1257 1 ≈ < SR f Offset and Gain Error Results Table 4 shows the offset error measured (in LSBs) for each of the channels in each gain configuration for the circuit in Figure 1. Table 4 also shows the average offset error of all of the channels for each gain configuration. The offset errors were measured by grounding all of the channel inputs and collecting and averaging 32,768 samples taken on each of the channels in each gain configuration. Table 4. Offset Error Measurements for all Channels and Gain Configurations (Error in LSBs) Gain Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel Average 0.4 1.34 1.33 1.31 1.36 1.44 1.45 1.46 1.48 1.40 0.8 1.98 1.99 2.02 2.06 2.00 1.98 1.99 1.97 2.00 1.6 3.25 3.19 3.22 3.19 3.17 3.08 3.13 3.14 3.17 3.2 5.57 5.66 5.67 5.55 5.57 5.50 5.54 5.52 5.57 XSC1 A B C D G T NOT U1 C2 40pF CNV PHASE 0V 3.3V 300ns 10µs V1 0V 4V 5µs 10µs CNV ADC_IN R2 400Ω S1 + – C1 120pF V1 RC_EXT R1 200Ω TIME (µs) ADC_IN V1 4.0V 4.0V 3.3V 4.0V CNV RC_EXT 711ns, 4V |
Codice articolo simile - AD8475 |
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Descrizione simile - AD8475 |
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