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ADF4355-2BCPZ-RL7 Scheda tecnica(PDF) 4 Page - Analog Devices |
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ADF4355-2BCPZ-RL7 Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 38 page Data Sheet ADF4355-2 Rev. B | Page 3 of 37 REVISION HISTORY 1/16—Rev. A to Rev. B Added Doubler Enabled Parameter to Table 1..............................4 Changes to Table 2 ............................................................................6 Changes to Table 3 ............................................................................7 Changes to Reference Input Section and INT, FRAC, MOD, and R Counter Relationship Section ....................................................13 Changes to Figure 25 ......................................................................14 Changes to Automatic Calibration Section .................................19 Changes to Reference Doubler Section and Figure 34...............23 Changes to Negative Bleed Section...............................................25 Changes to Loss of Lock Mode Section........................................27 Changes to ADC Clock Divider (ADC_CLK_DIV) ..................29 Changes to Register Initialization Sequence Section .................30 Changes to Frequency Update Sequence Section .......................31 Changes to Power Supplies Section and Figure 45 .....................35 2/15—Rev. 0 to Rev. A Changes to General Description Section .......................................1 Changes to Table 1 ............................................................................3 Changes to Absolute Maximum Ratings Section..........................6 Changes to Table 4 ............................................................................8 Changes to Figure 21 Caption .......................................................11 Changes to Reference Input Section and INT, FRAC, MOD, and R Counter Relationship Section ....................................................12 Changes to Figure 25 and Input Shift Registers Section............13 Changes to VCO Section and Output Stage Section..................14 Changes to Figure 28 ......................................................................16 Changes to Figure 30 and Automatic Calibration (Autocal) Section ..............................................................................................18 Changes to Figure 32 ......................................................................20 Changes to Phase Resync Section .................................................21 Changes to Figure 34 ......................................................................22 Changes to Reference Mode Section, Counter Reset Section, Register 5 Section, and Figure 35..................................................23 Changes to Negative Bleed Section and Feedback Select Section..24 Changes to Figure 38 Caption and Register 8 Section ...............27 Changed ADC Conversion Clock (ADC_CLK) Section to ADC Clock Divider (ADC_CLK_DIV) Section...................................28 Changes to ADC Clock Divider (ADC_CLK_DIV) Section....28 Changes to Register Initialization Sequence Section and Frequency Update Sequence Section............................................29 Changes to RF Synthesizer—A Worked Example Section ........30 Changes to Lock Time Section......................................................31 Added Lock Time—A Worked Example Section .......................31 Changes to Figure 45 ......................................................................33 10/14—Revision 0: Initial Version |
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