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HCPL-0661 Scheda tecnica(PDF) 3 Page - Agilent(Hewlett-Packard) |
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HCPL-0661 Scheda tecnica(HTML) 3 Page - Agilent(Hewlett-Packard) |
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3 / 10 page  3 Description These dual channel devices are optically coupled logic gates that combine GaAsP light emitting diodes and integrated high gain photodetectors. The photons are collected in the detector by a photodiode and the current is amplified by a high gain linear amplifier that drives a Schottky clamped open collector output transistor. Each circuit is temperature, current and voltage compensated. The internal shield provides a guaranteed common mode transient immunity specification of 5000 V/ µs for the HCPL- 2631/0631, and 10,000 V/ µs for the HCPL-4661/0661. These dual channel optocouplers are available in an 8 Pin DIP and in an industry standard SOIC-8 package. The following is a cross reference table listing the 8 Pin DIP part number and the electrically equivalent SOIC-8 part number. SOIC-8 8 Pin DIP Package HCPL-2630 HCPL-0630 HCPL-2631 HCPL-0631 HCPL-4661 HCPL-0661 The SOIC-8 does not require “through holes” in a PCB. This package occupies approximately one-third the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The unique design provides maximum ac and dc circuit isolation while achieving LSTTL and TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40 °C to +85 °C. The dual channel design minimizes PCB space. These devices are recommended for high speed logic interfacing, input/output buffering, and for use as line receivers in environ- ments that conventional line receivers cannot tolerate. They can be used for the digital programming of machine control systems, motors and floating power supplies. The internal shield makes the HCPL-2631/0631/4661/0661 ideal for use in extremely high ground or induced noise environments. Applications • Isolation of High Speed Logic Systems • Microprocessor System Interfaces • Isolated Line Receiver • Computer-Peripheral Interfaces • Ground Loop Elimination • Digital Isolation for A/D, D/A Conversion • Power Transistor Isolation in Motor Drives Schematic I F 2 HCPL-2631/0631/4661/0661 SHIELD 6 5 GND 3 4 VO2 V F 2 I O2 USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 1). + – I F 1 8 7 VCC 1 2 VO1 ICC V F 1 I O1 – + |
Codice articolo simile - HCPL-0661 |
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