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MC145745 Scheda tecnica(PDF) 9 Page - Motorola, Inc |
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MC145745 Scheda tecnica(HTML) 9 Page - Motorola, Inc |
9 / 16 page MC145745 MOTOROLA 9 DEVICE DESCRIPTION The MC145745 is a selectable modem chip compatible with V.21 (300 baud full duplex asynchronous) and V.23 mode 2 (1200 baud half duplex asynchronous). This device includes a DTMF generator, DTMF receiver, call–progress tone detector, answer tone generator, and a receive timing control circuit. The built–in differential line driver has the capability of driving 0 dBm into a 600 Ω load with a 5.0 V single power supply. The MC145745 also includes a serial control port (SCP) that permits an MCU to exercise the built– in features. The MC145745 provides an SCP interface to access an in- ternal byte register which controls the device operations; such as function mode, carrier detect timing, transmit/receive gain, and transmit tones. The transmit and receive amplifiers’ gain is programmable by SCP register setting (BR4). The TLA pin is also available to adjust the transmit level that is determined by the resistor (RTLA) value connected between the pin and GND. The DTMF receiver amplifier includes a built–in AGC amplifier which automatically adjusts the input amplifier gain corre- sponding to the amplitude of the DTMF tone input signal. The AGC dynamic range can be selected in four options. The highest received sensitivity obtained is approximately – 50 dBm when the dynamic range of the AGC amplifier is maximized. The tone generator, which can generate 16 DTMF tones, is used at the terminal for transmission of the call and control tones. In addition, a single tone can be generated for tests and other uses. Power down is amenable to software control by setting the byte register BR2. While the device is in the power down state, SCP still operates independently. There are two power down options available: power down 1 (the system clock operates alone) and power down 2 (the system clock stops). The clock generator constitutes an oscillation circuit with a 3.58 MHz crystal connected between the X1 and X2 pins. This device also has a 7.15909 MHz external clock input (ECLK), which has a clock divider circuit for providing a 3.58 MHz clock to the internal circuits. If the ECLK pin is used, the X2 pin should be held low. If the oscillation circuit (X1 and X2) is used, the ECLK pin should be held low. This device also has a clock buffer output (CLKO), which can be used for providing a 3.58 MHz clock to the external device. Table 1 shows the clock input and output relations in the dif- ferent modes. Table 1. Clock Selection Truth Table Fi M d Input Output Function Mode ECLK (Pin 12) X2 (Pin 11) CLKO (Pin 9) PD 1 0 fxtal fxtal Power Down 1 fext 0 fext/2 PD 2 0 X 0 Power Down 2 fext 0 0 Oh M d 0 fxtal fxtal Other Mode fext 0 fext/2 SERIAL CONTROL PORT (SCP INTERFACE) The MC145745 is equipped with an SCP. The SCP is a full–duplex four–wire interface with control and status in- formation passed to and from the internal register. The SCP is compatible with the Serial Peripheral Interface (SPI) of single chip MCUs used in other standard Motorola devices. The SCP consists of SCP Tx, SCP Rx, SCPCLK, and SCPEN for transmitting control data, status data, and DTMF receive data between the MCU and the MC145745. The SCPCLK determines the transmission and reception data rates, and the SCPEN governs when the data transaction is to take place. The operation/configuration of the MC145745 is pro- grammed by setting the state of the internal register bit. The control, status, and data information resides in 4–bit wide registers which are accessed via the 8–bit SCP bus transac- tion. The first four bits of the 8–bit bus transaction are the read/ write direction and the register address. The next four bits are the data written to or read from the internal registers. The SCP interface is independent of the 3.58 MHz master clock. It runs by using SCPCLK as the synchronizing signal. SCP TRANSACTION The SCP interface includes both read and write capabili- ties, which together comprise the SCP transaction. These SCP transaction functionalities are described below. SCP Read The SCP read action transaction is shown in Figure 5. Dur- ing the SCP read action, the SCPEN pin must be in the low position. After SCPEN high goes low, then at the first four SCPCLK rising edges, Read/Write (R/W) bit and three ad- dress bits (A0 – A2) are shifted into the intermediate buffer register. If the read action is to be performed, the R/W bit must be at 1. And then, at the following four SCPCLK falling edges, the 4–bit chosen register data is shifted out on SCP Tx. SCPEN must be restored to high after this trans- action, before another falling edge of SCPCLK is en- countered. While SCP Tx is in output mode, SCP Rx is disregarded. Also, whenever SCP Tx is not transmitting data, a high impedance condition is maintained. SCP Write The SCP write action transaction is shown in Figure 6. During the SCP write action, the SCPEN pin must be in the low position. After SCPEN high goes low, then at the first four SCPCLK rising edges, R/W and three address bits (A0 – A2) are shifted into the intermediate buffer register. If the write action is to be performed, the R/W bit must be at 0. And then, at the following four SCPCLK rising edges, the 4–bit data is shifted in from SCP Rx and written into the chosen register. During the write operation, SCP Tx is in high impedance. If the chosen register and/or the chosen bit are “read only,” the write action to it has no effect. |
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