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MC10170 Scheda tecnica(PDF) 1 Page - Motorola, Inc |
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MC10170 Scheda tecnica(HTML) 1 Page - Motorola, Inc |
1 / 4 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3–103 REV 6 © Motorola, Inc. 1996 9/96 9+2-Bit Parity Generator/ Checker The MC10170 is a 11–bit parity circuit, which is segmented into 9 data bits and 2 control bits. Output A generates odd parity on 9 bits; that is, Output A goes high for an odd number of high logic levels on the bit inputs in only 2 gate delays. The Control Inputs can be used to expand parity to larger numbers of bits with minimal delay or can be used to generate even parity. To expand parity to larger words, the MC10170 can be used with the MC10160 or other MC10170’s. The MC10170 can generate both even and odd parity. PD = 300 mW typ/pkg (No Load) tpd = 2.5 ns typ(Control Inputs to B Output) 4.0 ns typ (Data Inputs to A Output) 6.0 ns typ (Data Inputs to B Output) tr,tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 2 A ODD PARITY 15 B EVEN PARITY 13 HIGH 14 LOW 3 D0 4 D1 5 D2 6 D3 7 D4 9 D5 10 D6 11 D7 12 D8 CONTROL INPUTS INPUTS OUTPUTS Sum of Odd Parity Even Parity Sum of D Inp ts Odd Parity Even Parity D Inputs at High Level Output A Output B Even Low High Odd High Low MC10170 PIN ASSIGNMENT VCC1 A D0 D1 D2 D3 D4 VEE VCC2 B LOW HIGH D8 D7 D6 D5 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 |
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