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ISL15100 Scheda tecnica(PDF) 5 Page - Intersil Corporation |
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ISL15100 Scheda tecnica(HTML) 5 Page - Intersil Corporation |
5 / 9 page ISL15100 5 FN8577.0 September 19, 2013 Inverting Input Bias Current Mismatch IB-DM Difference between the INA- and INB- input bias currents -35 0 35 µA Inverting Input Bias Current Common Mode IB-CM Average inverting input bias currents (Note 7) -90 -30 55 µA Input Offset Voltage VIOA, VIOB Voltage difference from INA+ to INA- and from INB+ to INB- -85 0 85 mV Input Offset Voltage Mismatch VIODM VIOA - VIOB -5 0 5 mV Input Offset Voltage Common Mode VIOCM Average offset voltage across the two inputs -80 20 80 mV Differential Mode Output Offset Voltage VOSDM Output referred total effect of all differential DC error terms -7.8 0 7.8 mV Common Mode Output Offset Voltage VOSCM Output referred total effect of all common mode DC errors -105 40 145 mV Input Headroom to Positive Supply (VS+) - VIN(MAX) INA+ and INB+ required margin to VS+ supply 3V Input Headroom to Negative Supply VIN(MIN) - (VS-) INA+ and INB+ required margin to VS- supply 3V OUTPUT CHARACTERISTICS Output Swing VO-OPEN VS = ±6V, Differential RLOAD ≥ 1kΩ, each output pin voltage range ±4.85 ±5.0 V VO-LOADED VS = ±6V, VO in linear region, Differential RLOAD = 29Ω, each output pin voltage range. ±4.6 V VS = ±6V, VO driven into the rail, differential RLOAD = 29Ω, each output pin voltage range. ±4.2 ±4.7 V Output Current IO Linear output current (not short circuit) ±300 ±400 mA POWER SUPPLY Bipolar Supply Range ±VS Symmetric supply, pin 4 at GND for logic reference ±4 ±6 ±6.6 V Single Supply Range VS+Single supply with VS- and pin 4 at GND 8 12 13.2 V Positive Supply Currents IS+ (Full bias) VO(DIFF) = 0V, C0 = C1 = 0V 27 32 37 mA IS+ (Medium bias) VO(DIFF) = 0V, C0 = 3.3V, C1 = 0V 19 23 26 mA IS+ (Low bias) VO(DIFF) = 0V, C0 = 0V, C1 = 3.3V 12 15 18 mA IS+ (Power down) C0 = C1 = 3.3V 5.5 7 8.5 mA C0, C1 Input High Current IINH, C0 or C1 C0 = C1 = 3.3V (Note 7) -150 -90 -30 µA C0, C1 Input Low Current IINL, C0 or C1 C0 = C1 = 0V (Note 7) -1.5 1 1.5 µA C0, C1 Logic High Voltage VINH Pin 4 at GND, logic reference pin 2 3.3 5.5 V C0, C1 Logic Low Voltage VINL Pin 4 at GND, logic reference pin -0.3 0 0.8 V NOTES: 6. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design. 7. Positive currents flow out of the pin. Electrical Specifications VS+ = +12V, VS- = GND = 0V, see Figure 3, Full Bias (C0 = C1 = 0V), TA = +25°C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT |
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