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SI53340-B-GM Scheda tecnica(PDF) 1 Page - Silicon Laboratories |
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SI53340-B-GM Scheda tecnica(HTML) 1 Page - Silicon Laboratories |
1 / 38 page Si53340-45 Data Sheet Low-Jitter LVDS Fanout Clock Buffers with up to 10 LVDS Out- puts from Any-Format Input and Wide Frequency Range from dc up to 1250 MHz The Si53340-45 family of LVDS fanout buffers is ideal for clock/data distribution and re- dundant clocking applications. These devices feature typical ultra-low jitter of 50 fs and operate over a wide frequency range from dc to 1250 MHz. Built-in LDOs deliver high PSRR performance and reduces the need for external components simplifying low jitter clock distribution in noisy environments. They are available in multiple configurations and offer a selectable input clock using a 2:1 input mux. Other features include independent output enable and built-in format translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance. KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 LVDS Outputs • Any-format Inputs (LVPECL, Low-Power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range: dc to 1250 MHz • Output Enable option • Multiple configuration options • 2:1 Input Mux • RoHS compliant, Pb-free • Temperature range: –40 to +85 °C 0 1 CLK0* CLK1* CLK_SEL *Si53341/43/45 require Single-ended Inputs Si53342/43 Power Supply Filtering VDD 4 Outputs 10 Outputs 4 10 3 Outputs 3 Outputs 3 3 OEAb OEBb VDDOA VDDOB Si53340/41 Si53344/45 silabs.com | Smart. Connected. Energy-friendly. Rev. 1.2 |
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