MOTOROLA CMOS LOGIC DATA

3

MC14544B

Characteristic

Symbol

VDD

Min

Typ

Max

Unit

Output Rise Time

tTLH = (3.0 ns/pF) CL + 30 ns

tTLH = (1.5 ns/pF) CL + 15 ns

tTLH = (1.1 ns/pF) CL + 10 ns

tTLH

5.0

10

15

—

—

—

100

50

40

200

100

80

ns

Output Fall Time

tTHL = (1.5 ns/pF) CL + 25 ns

tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 12.5 ns

tTHL

5.0

10

15

—

—

—

100

50

40

200

100

80

ns

Turn–Off Delay Time

tPLH = (1.7 ns/pF) CL + 520 ns

tPLH = (0.66 ns/pF) CL + 217 ns

tPLH = (0.5 ns/pF) CL + 160 ns

tPLH

5.0

10

15

—

—

—

605

250

185

1210

500

370

ns

Turn–On Delay Time

tPHL = (1.7 ns/pF) CL + 420 ns

tPHL = (0.66 ns/pF) CL + 172 ns

tPHL = (0.5 ns/pF) CL + 130 ns

tPHL

5.0

10

15

—

—

—

505

205

155

1650

660

495

ns

Setup Time

tsu

5.0

10

15

0

0

0

– 40

– 15

– 10

—

—

—

ns

Hold Time

th

5.0

10

15

80

30

20

40

15

10

—

—

—

ns

Latch Disable Pulse Width (Strobing Data)

tWH

5.0

10

15

250

100

80

125

50

40

—

—

—

ns

* The formulas given are for the typical characteristics only.

LOGIC DIAGRAM

VDD = PIN 18

VSS = PIN 9

B 3

LD 1

D 4

C 2

A 5

6

PHASE

16 g

17 f

15 e

14 d

13 c

12 b

11 a

BI 7

8 RBO

RBI 10