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ADF4356BCPZ Scheda tecnica(PDF) 7 Page - Analog Devices |
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ADF4356BCPZ Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 35 page Data Sheet ADF4356 Rev. 0 | Page 7 of 35 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. NIC = NOT INTERNALLY CONNECTED. 2. THE EXPOSED PAD MUST BE CONNECTED TO AGND. 24 23 22 21 20 19 18 17 VBIAS VREF NIC AGNDVCO VTUNE VREGVCO AGNDVDO VVCO 1 2 3 4 5 6 7 8 CLK DATA LE CE AVDD VP CPOUT CPGND ADF4356 TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 2 DATA Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four LSBs as the control bits. This input is a high impedance CMOS input. 3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is selected by the four LSBs. 4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A logic high on this pin powers up the device, depending on the status of the power-down bits. 5, 16 AVDD Analog Power Supplies. These pins range from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog ground plane as close to these pins as possible. AVDD must have the same value as DVDD. 6 VP Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground plane as close to this pin as possible. 7 CPOUT Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the loop filter is connected to VTUNE to drive the internal VCO. 8 CPGND Charge Pump Ground. This output is the ground return pin for CPOUT. 9 AGND Analog Ground. This pin is the ground return pin for AVDD. 10 VRF Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin as possible. VRF must have the same value as AVDD. 11 RFOUTA+ VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. 12 RFOUTA− Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. 13 AGNDRF RF Output Stage Ground. This pin is the ground return pin for the RF output stage. 14 RFOUTB+ Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. 15 RFOUTB− Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available. 17 VVCO Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to the analog ground plane as close to this pin as possible. 18, 21 AGNDVCO VCO Ground. This pin is the ground return path for the VCO. 19 VREGVCO VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible. Connect VREGVCO directly to VVCO. |
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