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AD6684BCPZRL7-500 Scheda tecnica(PDF) 4 Page - Analog Devices

Il numero della parte AD6684BCPZRL7-500
Spiegazioni elettronici  135 MHz Quad IF Receiver
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD6684BCPZRL7-500 Scheda tecnica(HTML) 4 Page - Analog Devices

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AD6684
Data Sheet
Rev. 0 | Page 4 of 107
GENERAL DESCRIPTION
The AD6684 is a 135 MHz bandwidth, quad intermediate
frequency (IF) receiver. It consists of four 14-bit, 500 MSPS
ADCs and various digital processing blocks consisting of four
wideband DDCs, an NSR, and VDR monitoring. The device has
an on-chip buffer and a sample-and-hold circuit designed for low
power, small size, and ease of use. This device is designed to
support communications applications. The analog full power
bandwidth of the device is 1.4 GHz.
The quad ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. The AD6684 is optimized for wide
input bandwidth, excellent linearity, and low power in a small
package.
The analog inputs and clock signal input are differential. Each
pair of ADC data outputs are internally connected to two DDCs
through a crossbar mux. Each DDC consists of up to five cascaded
signal processing stages: a 48-bit frequency translator, NCO, and
up to four half-band decimation filters.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
serial port interface (SPI). With the NSR feature enabled, the
outputs of the ADCs are processed such that the AD6684
supports enhanced SNR performance within a limited portion
of the Nyquist bandwidth while maintaining a 9-bit output
resolution.
Each ADC output is also connected internally to a VDR block.
This optional mode allows full dynamic range for defined input
signals. Inputs that are within a defined mask (based on DPD
applications) are passed unaltered. Inputs that violate this
defined mask result in the reduction of the output resolution.
With VDR, the dynamic range of the observation receiver is
determined by a defined input frequency mask. For signals
falling within the mask, the outputs are presented at the
maximum resolution allowed. For signals exceeding defined
power levels within this frequency mask, the output resolution
is truncated. This mask is based on DPD applications and
supports tunable real IF sampling, and zero IF or complex IF
receive architectures.
Operation of the AD6684 in the DDC, NSR, and VDR modes is
selectable via SPI-programmable profiles (the default mode is
NSR at startup).
In addition to the DDC blocks, the AD6684 has several functions
that simplify the AGC function in the communications receiver.
The programmable threshold detector allows monitoring of the
incoming signal power using the fast detect output bits of the
ADC. If the input signal level exceeds the programmable threshold,
the fast detect indicator goes high. Because this threshold
indicator has low latency, the user can quickly turn down the
system gain to avoid an overrange condition at the ADC input.
Users can configure each pair of IF receiver outputs onto either
one or two lanes of Subclass 1 JESD204B-based high speed
serialized outputs, depending on the decimation ratio and the
acceptable lane rate of the receiving logic device. Multiple device
synchronization is supported through the SYSREF±,
SYNCINB±AB, and SYNCINB±CD input pins.
The AD6684 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using the 1.8 V capable, 3-wire SPI.
The AD6684 is available in a Pb-free, 72-lead LFCSP and is
specified over the −40°C to +105°C junction temperature range.
This product may be protected by one or more U.S. or international
patents
PRODUCT HIGHLIGHTS
1.
Low power consumption per channel.
2.
JESD204B lane rate support up to 15 Gbps.
3.
Wide full power bandwidth supports IF sampling of signals
up to 1.4 GHz.
4.
Buffered inputs ease filter design and implementation.
5.
Four integrated wideband decimation filters and NCO
blocks supporting multiband receivers.
6.
Programmable fast overrange detection.
7.
On-chip temperature diode for system thermal management.


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