AD4000

Data Sheet

Rev. 0 | Page 4 of 32

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

−3 dB Input Bandwidth

10

MHz

Aperture Delay

1

ns

Aperture Jitter

1

ps rms

REFERENCE

2.4

5.1

V

Current

0.75

mA

OVERVOLTAGE CLAMP

50

mA

50

mA

5.4

V

3.1

V

5.25

5.4

V

2.68

2.8

V

Deactivation Time

360

ns

100

µA

DIGITAL INPUTS

Logic Levels

VIO > 2.7 V

−0.3

+0.3 × VIO

V

VIO ≤ 2.7 V

−0.3

+0.2 × VIO

V

VIO > 2.7 V

0.7 × VIO

VIO + 0.3

V

VIO ≤ 2.7 V

0.8 × VIO

VIO + 0.3

V

−1

+1

µA

−1

+1

µA

Input Pin Capacitance

6

pF

DIGITAL OUTPUTS

Data Format

Serial 16 bits, straight binary

Pipeline Delay

Conversion results available immediately

after completed conversion

0.4

V

VIO − 0.3

V

POWER SUPPLIES

VDD

1.71

1.8

1.89

V

VIO

1.71

5.5

V

Standby Current

VDD and VIO = 1.8 V, T = 25°C

1.6

µA

Power Dissipation

10 kSPS, high-Z mode disabled

70

µW

1 MSPS, high-Z mode disabled

7

mW

2 MSPS, high-Z mode disabled

14

16

mW

1 MSPS, high-Z mode enabled

8

mW

2 MSPS, high-Z mode enabled

16

19

mW

VDD Only

2 MSPS, high-Z mode disabled

9.75

mW

REF Only

2 MSPS, high-Z mode disabled

3.75

mW

VIO Only

2 MSPS, high-Z mode disabled

0.5

mW

Energy per Conversion

7

nJ/sample

TEMPERATURE RANGE

Specified Performance

−40

+125

°C

1

The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.

2

A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable

throughput for different modes of operation.

3

Transient response is the time required for the ADC to acquire a full scale input step to ±0.5 LSB accuracy.

4

The minimum and maximum values are guaranteed by characterization, not production tested.

5

See the 1/f noise plot in Figure 18.