MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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High Frequency Clock Generator

The MC12430 is a general purpose synthesized clock source targeting

applications that require both serial and parallel interfaces. Its internal

VCO will operate over a range of frequencies from 400 to 800MHz. The

differential PECL output can be configured to be the VCO frequency

divided by 1, 2, 4 or 8. With the output configured to divide the VCO

frequency by 2, and with a 16.000MHz external quartz crystal used to

provide the reference frequency, the output frequency can be specified in

1MHz steps. The PLL loop filter is fully integrated so that no external

components are required.

Functional Description

The internal oscillator uses the external quartz crystal as the basis of

its frequency reference. The output of the reference oscillator is divided

by 8 before being sent to the phase detector. With a 16MHz crystal, this

provides a reference frequency of 2MHz. Although this data sheet

illustrates functionality only for a 16MHz crystal, any crystal in the

10–20MHz range can be used.

The VCO within the PLL operates over a range of 400 to 800MHz. Its output is scaled by a divider that is configured by either

the serial or parallel interfaces. The output of this loop divider is applied to the phase detector.

The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by

adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.

The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider

(N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4 or 8).

This divider extends performance of the part while providing a 50% duty cycle.

The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated

in 50

Ω to VCC – 2.0. The positive reference for the output driver and the internal logic is separated from the power supply for the

phase–locked loop to minimize noise induced jitter.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]

inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power

becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority

over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the

application of the chip.

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.

The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The

configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the

programming section for more information.

The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the

programming section for more information.

MC12430

HIGH FREQUENCY PLL

CLOCK GENERATOR

FN SUFFIX

28–LEAD PLCC PACKAGE

CASE 776–02

FA SUFFIX

32–LEAD TQFP PACKAGE

CASE 873A–02