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MC12430 Scheda tecnica(PDF) 5 Page - Motorola, Inc |
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MC12430 Scheda tecnica(HTML) 5 Page - Motorola, Inc |
5 / 12 page MC12430 TIMING SOLUTIONS BR1333 — Rev 6 5 MOTOROLA Figure 2. Serial Test Clock Block Diagram FDIV4 MCNT LOW FOUT MCNT FREF HIGH TEST MUX 7 0 TEST FOUT (VIA ENABLE GATE) N DIVIDE (1, 2, 4, 8) 0 1 PLL 12430 LATCH Reset PLOADB M COUNTER SLOAD T0 T1 T2 VCO_CLK SHIFT REG 14–BIT DECODE SDATA SCLOCK MCNT FREF SEL_CLK • T2=T1=1, T0=0: Test Mode • SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin. DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V to 5.0V ±5%) Symbol Characteristic Min Typ Max Unit Condition VIH Input HIGH Voltage 2.0 V VCC = 3.3 to 5.0V VIL Input LOW Voltage 0.8 V VCC = 3.3 to 5.0V IIN Input Current 1.0 mA VOH Output HIGH Voltage 2.17 2.50 V VCC0 = 3.3V1 VOL Output LOW Voltage 1.41 1.76 V VCC0 = 3.3V1 ICC Power Supply Current VCC PLL_VCC 85 15 100 20 mA 1. Output levels will vary 1:1 with VCC0 variation. |
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