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2N2222A Scheda tecnica(PDF) 4 Page - M/A-COM Technology Solutions, Inc.

Il numero della parte 2N2222A
Spiegazioni elettronici  Radiation Hardened NPN Silicon Switching Transistors
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Produttore elettronici  MA-COM [M/A-COM Technology Solutions, Inc.]
Homepage  http://www.macomtech.com
Logo MA-COM - M/A-COM Technology Solutions, Inc.

2N2222A Scheda tecnica(HTML) 4 Page - M/A-COM Technology Solutions, Inc.

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Radiation Hardened NPN Silicon Switching Transistors
Rev. V1
2N2221A, L, UA, UB &
2N2222A, L, UA, UB
4
4
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
https://www.macom.com/support
4
Outline Drawing (UA Surface Mount):
Symbol
Dimensions
Notes
Inches
Millimeters
Min.
Max.
Min.
Max.
BL
0.215
0.225
5.46
5.71
BL2
0.225
5.71
BW
0.145
0.155
3.68
3.93
BW2
0.155
3.93
CH
0.061
0.075
1.55
1.90
3
L3
0.003
0.007
0.08
0.18
5
LH
0.029
0.042
0.74
1.07
LL1
0.032
0.048
0.81
1.22
LL2
0.072
0.088
1.83
2.23
LS
0.045
0.055
1.14
1.39
LW
0.022
0.028
0.56
0.71
LW2
0.006
0.022
0.15
0.56
5
1. Dimensions are in inches.
2. Millimeters are given for general information only.
3. Dimension CH controls the overall package thickness. When a window lid is used, dimension CH must
increase by a minimum of .010 inch (0.254 mm) and a maximum of .040 inch (1.020 mm).
4. The corner shape (square, notch, radius) may vary at the manufacturer's option, from that shown on the
drawing.
5. Dimensions LW2 minimum and L3 minimum and the appropriate castellation length define an unobstructed
three-dimensional space traversing all of the ceramic layers in which a castellation was designed.
(Castellations are required on the bottom two layers, optional on the top ceramic layer.) Dimension LW2
maximum and L3 maximum define the maximum width and depth of the castellation at any point on its
surface. Measurement of these dimensions may be made prior to solder dipping.
6. The co-planarity deviation of all terminal contact points, as defined by the device seating plane, shall not
exceed .006 inch (0.15 mm) for solder dipped leadless chip carriers.
7. In accordance with ASME Y14.5M, diameters are equivalent to Фx symbology.
Pin #
1
2
3
4
Transistor Collector
Emitter
Base
N/C


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