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74HC541A Scheda tecnica(PDF) 4 Page - Motorola, Inc |
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74HC541A Scheda tecnica(HTML) 4 Page - Motorola, Inc |
4 / 6 page MC54/74HC541A MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 3–4 CL* *Includes all probe and jig capacitance TEST POINT DEVICE UNDER TEST OUTPUT TEST CIRCUITS Figure 3. Figure 4. CL* *Includes all probe and jig capacitance TEST POINT DEVICE UNDER TEST OUTPUT 1k Ω CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH. PIN DESCRIPTIONS INPUTS A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9) — Data input pins. Data on these pins appear in non–in- verted form on the corresponding Y outputs, when the out- puts are enabled. CONTROLS OE1, OE2 (PINS 1, 19) — Output enables (active–low). When a low voltage is applied to both of these pins, the out- puts are enabled and the device functions as an non–invert- ing buffer. When a high voltage is applied to either input, the outputs assume the high impedance state. OUTPUTS Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14, 13, 12, 11) — Device outputs. Depending upon the state of the output enable pins, these outputs are either non–invert- ing outputs or high–impedance outputs. VCC To 7 Other Buffers LOGIC DETAIL One of Eight Buffers INPUT A OE1 OE2 OUTPUT Y |
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