Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

FM30C256 Scheda tecnica(PDF) 9 Page - List of Unclassifed Manufacturers

Il numero della parte FM30C256
Spiegazioni elettronici  256Kb Data Collector
Download  18 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  ETC [List of Unclassifed Manufacturers]
Homepage  
Logo ETC - List of Unclassifed Manufacturers

FM30C256 Scheda tecnica(HTML) 9 Page - List of Unclassifed Manufacturers

Back Button FM30C256 Datasheet HTML 5Page - List of Unclassifed Manufacturers FM30C256 Datasheet HTML 6Page - List of Unclassifed Manufacturers FM30C256 Datasheet HTML 7Page - List of Unclassifed Manufacturers FM30C256 Datasheet HTML 8Page - List of Unclassifed Manufacturers FM30C256 Datasheet HTML 9Page - List of Unclassifed Manufacturers FM30C256 Datasheet HTML 10Page - List of Unclassifed Manufacturers FM30C256 Datasheet HTML 11Page - List of Unclassifed Manufacturers FM30C256 Datasheet HTML 12Page - List of Unclassifed Manufacturers FM30C256 Datasheet HTML 13Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 18 page
background image
FM30C256
Rev 2.1
Dec. 2002
Page 9 of 18
Two-wire Interface
The FM30C256 employs an industry standard two-
wire bus that is familiar to many users and for
convenience is described in this section.
The FM30C256 is unique since it incorporates two
logical devices in one chip. Each logical device can
be accessed individually. One is a memory device. It
has a Slave Address (Slave ID = 1010b) that
operates the same as a stand-alone memory device.
The second device is a real-time clock and tamper
detect which share a unique Slave Address (Slave
ID = 1101b).
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM30C256 is always a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions:
Start, Stop, Data bit, and Acknowledge. Figure 4
illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the
electrical specifications.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM30C256 for a new operation.
If the power supply drops below the specified VDD
minimum during operation, the system should issue a
Start condition prior to performing another operation.
Stop Condition
A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal
is high. All operations must end with a Stop
condition. If an operation is pending when a stop is
asserted, the operation will be aborted. The master
must have control of SDA (not a memory read) in
order to assert a Stop condition.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The Acknowledge takes place after the 8th data bit
has been transferred in any transaction. During this
state the transmitter must release the SDA bus to
allow the receiver to drive it. The receiver drives the
SDA signal low to acknowledge receipt of the byte.
If the receiver does not drive SDA low, the
condition is a No-Acknowledge and the operation is
aborted.
The receiver might fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge ends the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
send an Acknowledge to deliberately terminate an
operation. For example, during a read operation, the
FM30C256 will continue to place data onto the bus
as long as the receiver sends Acknowledges (and
clocks). When a read operation is complete and no
more data is needed, the receiver must not
acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the
FM30C256 to attempt to drive the bus on the next
clock while the master is sending a new command
such as a Stop.
Stop
(Master)
Start
(Master)
7
Data bits
(Transmitter)
6
0
Data bit
(Transmitter)
Acknowledge
(Receiver)
SCL
SDA
Figure 3. Data Transfer Protocol


Codice articolo simile - FM30C256

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
RFE international
FM300 RFE-FM300 Datasheet
87Kb / 1P
   FUSIBLE RESISTORS FM, FKN, & FSQ Series: Fusible
logo
Extech Instruments Corp...
FM300 EXTECH-FM300 Datasheet
95Kb / 1P
   Desktop Formaldehyde (CH2O or HCHO) Monitor
logo
Rectron Semiconductor
FM3000 RECTRON-FM3000 Datasheet
217Kb / 7P
   GENERAL-PURPOSE PLASTIC RECTIFIERS
FM3000W RECTRON-FM3000W Datasheet
128Kb / 6P
   HIGH VOLTAGE RECTIFIER VOLTAGE RANGE 1200 to 3500 Volts CURRENT 0.2 to 0.5 Ampere
logo
SHENZHEN FUMAN ELECTRON...
FM3004 FUMAN-FM3004 Datasheet
153Kb / 4P
   USB charge controller
More results

Descrizione simile - FM30C256

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Advantech Co., Ltd.
ESRP-PCS-UNO420 ADVANTECH-ESRP-PCS-UNO420 Datasheet
814Kb / 2P
   Edge Data Collector
ESRP-PCS-WISE710 ADVANTECH-ESRP-PCS-WISE710 Datasheet
1Mb / 2P
   Edge Data Collector
SRP-IFS210-D36TAE ADVANTECH-SRP-IFS210-D36TAE Datasheet
312Kb / 2P
   Environment Data Collector
26-Jan-2022
ESRP-CNC-UNO1372 ADVANTECH-ESRP-CNC-UNO1372 Datasheet
1,009Kb / 2P
   Edge Data Collector
logo
Generalplus Technology ...
GPC252A GENERALPLUS-GPC252A Datasheet
438Kb / 17P
   256KB Sound Controller
GPL133A GENERALPLUS-GPL133A Datasheet
447Kb / 20P
   256KB LCD CONTROLLER
logo
Analog Devices
ADCLK914BCPZ-WP AD-ADCLK914BCPZ-WP Datasheet
304Kb / 12P
   Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer
REV. A
ADCLK914 AD-ADCLK914 Datasheet
302Kb / 11P
   Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer
logo
Renesas Technology Corp
R1LP5256E RENESAS-R1LP5256E_17 Datasheet
356Kb / 13P
   256Kb Advanced LPSRAM
logo
Generalplus Technology ...
GPC251A1 GENERALPLUS-GPC251A1 Datasheet
441Kb / 16P
   256KB Sound Controller
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com