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FM30C256 Scheda tecnica(PDF) 9 Page - List of Unclassifed Manufacturers |
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FM30C256 Scheda tecnica(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 18 page FM30C256 Rev 2.1 Dec. 2002 Page 9 of 18 Two-wire Interface The FM30C256 employs an industry standard two- wire bus that is familiar to many users and for convenience is described in this section. The FM30C256 is unique since it incorporates two logical devices in one chip. Each logical device can be accessed individually. One is a memory device. It has a Slave Address (Slave ID = 1010b) that operates the same as a stand-alone memory device. The second device is a real-time clock and tamper detect which share a unique Slave Address (Slave ID = 1101b). By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM30C256 is always a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions: Start, Stop, Data bit, and Acknowledge. Figure 4 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications. Start Condition A Start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high. All read and write transactions begin with a Start condition. An operation in progress can be aborted by asserting a Start condition at any time. Aborting an operation using the Start condition will ready the FM30C256 for a new operation. If the power supply drops below the specified VDD minimum during operation, the system should issue a Start condition prior to performing another operation. Stop Condition A Stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations must end with a Stop condition. If an operation is pending when a stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a Stop condition. Data/Address Transfer All data transfers (including addresses) take place while the SCL signal is high. Except under the two conditions described above, the SDA signal should not change while SCL is high. Acknowledge The Acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter must release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, the condition is a No-Acknowledge and the operation is aborted. The receiver might fail to acknowledge for two distinct reasons. First is that a byte transfer fails. In this case, the No-Acknowledge ends the current operation so that the part can be addressed again. This allows the last byte to be recovered in the event of a communication error. Second and most common, the receiver does not send an Acknowledge to deliberately terminate an operation. For example, during a read operation, the FM30C256 will continue to place data onto the bus as long as the receiver sends Acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM30C256 to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop. Stop (Master) Start (Master) 7 Data bits (Transmitter) 6 0 Data bit (Transmitter) Acknowledge (Receiver) SCL SDA Figure 3. Data Transfer Protocol |
Codice articolo simile - FM30C256 |
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Descrizione simile - FM30C256 |
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