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TP5510N Scheda tecnica(PDF) 2 Page - National Semiconductor (TI) |
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TP5510N Scheda tecnica(HTML) 2 Page - National Semiconductor (TI) |
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2 / 12 page  Block Diagram TLH11186 – 2 FIGURE 1 Pin Description Symbol Function VBB Negative power supply pin VBB eb5V g 5% GNDA Analog ground All signals are referenced to this pin VFDO Analog output of the receive power ampli- fier VCC Positive power supply pin VCC ea5V g 5% Symbol Function FSD Decode frame sync pulse which enables BCLKR to shift data into DD FSD is an 8 kHz pulse train See Figures 2 and 3 for timing details DD Decode data input Data is shifted into DD following the FSD leading edge BCLKD CLKSEL The bit clock which shifts data into DD af- ter the FSD leading edge May vary from 64 kHz to 2048 MHz Alternatively may be a logic input which selects either 1536 MHz1544 MHz or 2048 MHz for master clock in synchronous mode and BCLKD is used for both encode and de- code directions (see Table 1) http www nationalcom 2 |
Codice articolo simile - TP5510N |
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Descrizione simile - TP5510N |
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