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FM25160-P Scheda tecnica(PDF) 5 Page - List of Unclassifed Manufacturers |
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FM25160-P Scheda tecnica(HTML) 5 Page - List of Unclassifed Manufacturers |
5 / 14 page Ramtron FM25160 12 May 2000 5/14 Data Transfer All data transfers to and from the FM25160 occur in 8-bit groups. They are synchronized to the clock signal (SCK) and occur most significant bit (MSB) first. Serial inputs are clocked in on the rising edge of SCK. Outputs are driven on the falling edge of SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25160. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, are commands that have no subsequent operations. They perform a single function such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the status register Last are commands for memory transactions followed by address and one or more bytes of data. Table 1. Op-code Commands Name Description Op-code value WREN Set Write Enable Latch 00000110 WRDI Write Disable 00000100 RDSR Read Status Register 00000101 WRSR Write Status Register 00000001 READ Read Memory Data 00AAA011 WRITE Write Memory Data 00AAA010 WREN - Set Write Enable Latch The FM25160 will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the status register and writing the memory. Sending the WREN op-code causes the internal Write Enable Latch to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no affect. Completing any write operation will automatically clear the write enable latch and prevent further writes without another WREN command. Figure 4 below illustrates the WREN command bus configuration. WRDI - Write Disable The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the status register and verifying that WEL=0. Figure 5 below illustrates the WRDI command bus configuration. Figure 4. WREN Bus Configuration Figure 5. WRDI Bus Configuration |
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