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TPL0401A-10-Q1 Scheda tecnica(PDF) 5 Page - Texas Instruments

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Il numero della parte TPL0401A-10-Q1
Spiegazioni elettronici  128-TAPS Single-Channel Digital Potentiometer with I2C Interface
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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TPL0401A-10-Q1
TPL0401B-10-Q1
www.ti.com
SLIS182 – NOVEMBER 2016
Product Folder Links: TPL0401A-10-Q1 TPL0401B-10-Q1
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
Electrical Characteristics (continued)
Typical values are specified at 25°C and VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
INL = ((VMEAS[code x] – VMEAS[code 0]) / LSB) – [code x]
(2)
LSB = (VMEAS[code 127] – VMEAS[code 0]) / 127
(3)
DNL = ((VMEAS[code x] – VMEAS[code x-1]) / LSB) – 1
(4)
ZSERROR = VMEAS[code 0] / IDEAL_LSB
(5)
IDEAL_LSB = VH/ 128
(6)
FSERROR = [(VMEAS[code 127] – VH) / IDEAL_LSB] + 1
(7)
RINL = ( (RMEAS[code x] – RMEAS[code 0]) / RLSB) – [code x]
(8)
RLSB = (RMEAS[code 127] – RMEAS[code 0]) / 127
(9)
RDNL = ( (RMEAS[code x] – RMEAS[code x–1]) / RLSB ) – 1
(10) ROFFSET = RMEAS[code 0] / IDEAL_RLSB
(11) IDEAL_RLSB = RTOT / 128
CH
Terminal capacitance
10
pF
CW
Wiper capacitance
11
pF
TCR
Resistance temperature coefficient
22
ppm/°C
IDD(STBY)
VDD standby current
–40°C to +105°C
0.5
µA
–40°C to +125°C
1.5
IIN-DIG
Digital pins leakage current (SCL,
SDA Inputs)
–2.5
2.5
µA
SERIAL INTERFACE SPECS (SDA, SCL)
VIH
Input high voltage
0.7 ×
VDD
VDD
V
VIL
Input low voltage
0
0.3 ×
VDD
V
VOL
Output low voltage
SDA Pin, IOL = 4 mA
0.4
V
CIN
Pin capacitance
SCL, SDA Inputs
7
pF
VOLTAGE DIVIDER MODE (VH = VDD, VW = Not Loaded)
INL(1)(2)
Integral non-linearity
–0.5
0.5
LSB
DNL(3)(2)
Differential non-linearity
–0.25
0.25
LSB
ZSERROR
(4) (5)
Zero-scale error
0
0.75
1.5
LSB
FSERROR
(6) (5)
Full-scale error
–1.5
–0.75
0
LSB
TCV
Ratiometric temperature coefficient Wiper set at mid-scale
4
ppm/°C
BW
Bandwidth
Wiper set at mid-scale,
CLOAD = 10 pF
2862
kHz
TSW
Wiper settling time
See Figure 10
0.152
µs
THD+N
Total harmonic distortion
VH = 1 VRMS at 1 kHz,
measurement at W
0.03
%
RHEOSTAT MODE (VH = VDD, VW = Not Loaded)
RINL(7)(8)
Rheostat mode integral non-
linearity
–1
1
LSB
RDNL(9)(8)
Rheostat mode differential non-
linearity
0.5
0.5
LSB
ROFFSET
(10) (1
1)
Rheostat-mode zero-scale error
0
0.75
2
LSB
7.6 Timing Requirements
MIN
MAX
UNIT
STANDARD MODE
fSCL
I2C Clock frequency
0
100
kHz
tSCH
I2C Clock high time
4
µs
tSCL
I2C Clock low time
4.7
µs
tsp
I2C Spike time
0
50
ns
tSDS
I2C Serial data setup time
250
ns


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