LM2637 datasheet(10/17 Pages) NSC

Il numero della parte	LM2637

Spiegazioni elettronici	Motherboard Power Supply Solution with a 5-Bit Programmable Switching Controller and Two Linear Regulator Controllers

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Produttore elettronici	NSC [National Semiconductor (TI)]

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Applications Information (Continued)

will be low. There will also be a logic high signal at the OVP

pin that can be used to fire an external SCR. To clear this

mode, refer to the

Resetting the LM2637 section.

Linear Section — There is no over-voltage protection in the

linear controllers.

Under-Voltage Latch-Off

At the completion of soft start, the controller starts to monitor

all three output voltages. If any of the voltages goes below

about 0.63V, the controller will latch off its corresponding

section, i.e., switching or linear. The mode can be cleared by

following the procedures described in the

Resetting the

LM2637 section.

Current Limit

Switching Section — Current limit can be realized by two

methods. One method is through sensing the V

DS of the

high-side FET. The other is through a separate sense resis-

tor. The first method is cheaper and more power efficient but

less accurate. The second method is more accurate but dis-

sipates additional power and is either more expensive or re-

quires special PCB layout consideration. A side benefit of the

second method is it enables implementation of a technique

called dynamic voltage positioning, which helps save the

number of output capacitors.

The LM2637 tells in which current limit mode it is supposed

to be by detecting the CS+ pin voltage. When CS+ voltage is

1.2V below V

CC voltage, sense resistor method is assumed.

Otherwise the V

DS method is chosen. The VDS method is

based on typical r

DS_ON of the high-side FET and load cur-

rent levels.

Method 1 — High-Side FET VDS Sensing

This method detects the high-side FET drain current by

sensing its drain-source voltage when it is on. See

Figure 4.

Since the r

DS_ON of a FET is a known value, current through

the FET can be known by measuring its V

DS. The relation-

ship between the three parameters is:

(2)

To implement the current limit function, an external resistor

R

IMAX is needed. The resistor should be connected between

the drain of the high-side FET and IMAX pin. A constant cur-

rent of around 180 µA is forced to flow into the IMAX pin and

causes a fixed voltage drop across the R

IMAX resistor. This

voltage drop is then compared with the V

DS of the high-side

FET and if the latter is higher, over current is assumed. The

appropriate value of R

IMAX for a pre-determined current limit

level I

LIM can be determined by the following equation:

(3)

For example, suppose that the r

DS_ON of the FET is 20 mΩ,

and the desired current limit is 20A, then R

IMAX should be

2.2 k

Ω.

Notice however, that the r

DS_ON of the FET has a positive

temperature coefficient and it can increase by as much as

50% when heated up. Also the distribution of the r

DS_ON can

be fairly wide, a 1.25 to 1.5 ratio is not uncommon. Consult

the MOSFET vendor for further information on the distribu-

tion of r

DS_ON.

The designer should carefully choose the value of R

IMAX so

that even under the extreme case (largest r

DS_ON and high-

est temperature) the current limit will not trigger below the

preset value.

To provide the greatest protection over the high-side FET,

cycle-by-cycle protection is implemented. The sampling of

the V

DS starts as early as 250 ns after the FET is turned on.

Whenever an over-current condition is detected, the

high-side FET is immediately turned off and the low-side

FET turned on. This status remains for the rest of the cycle.

The same procedure applies to the next switching cycle. The

blanking time of 250 ns is to avoid the switching noise that

occurs whenever the FET is turned on.

The resistor between CS− pin and the switching node

(source of the high-side FET) is important for minimizing the

noise and negative voltage present at the CS− pin. A resis-

tance of 100

Ω to 300Ω is recommended.

Method 2 — Current Sense Resistor

This method uses a sense resistor in series with the output

inductor to detect the load current.

SeeFigure 5. The voltage

across the sense resistor is proportional to load current. In

the case that the sense resistor is of discrete type (i.e., not a

PCB etch resistor) or the sense resistor value is optimized

for dynamic voltage positioning (see the

Dynamic Position-

ing of Load Voltage section), it may be necessary to use two

signal level resistors, R

1 and R2 to appropriately set the de-

sired current limit.

DS100848-8

FIGURE 4. Current Limit via High-Side FET V

DS

Sensing

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