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CS8416-CS Scheda tecnica(PDF) 8 Page - Cirrus Logic |
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CS8416-CS Scheda tecnica(HTML) 8 Page - Cirrus Logic |
8 / 48 page CS8416 8 DS578PP2 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 to 5.5V, Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL =20 pF) Notes: 9. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dictated by the timing requirements necessary to access the Channel Status memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is 32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions. 10. Data must be held for sufficient time to bridge the transition time of CCLK. 11. For fsck <1 MHz. Parameter Symbol Min Max Unit CCLK Clock Frequency (Note 9)fsck 06.0 MHz CS High Time Between Transmissions tcsh 1.0 - µs CS Falling to CCLK Edge tcss 20 - ns CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 10)tdh 15 - ns CCLK Falling to CDOUT Stable tpd -50 ns Rise Time of CDOUT tr1 -25 ns Fall Time of CDOUT tf1 -25 ns Rise Time of CCLK and CDIN (Note 11) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 11)tr2 - 100 ns t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t pd CDOUT t csh Figure 3. SPI Mode Timing |
Codice articolo simile - CS8416-CS |
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Descrizione simile - CS8416-CS |
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