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CDCLVP111-EP Scheda tecnica(PDF) 3 Page - Texas Instruments |
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CDCLVP111-EP Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 23 page 28 VCC 18 VCC 29 Q2 17 VCC 30 Q2 16 Q7 31 Q1 15 Q7 32 Q1 14 Q8 33 Q0 13 Q8 34 Q0 12 Q9 35 VCC 11 Q9 36 VCC 10 VCC Not to scale 3 CDCLVP111-SP www.ti.com SCAS946 – NOVEMBER 2016 Product Folder Links: CDCLVP111-SP Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) CLKn, CLK_SEL pull down resistor = 75 k Ω; CLKn pull up resistor = 37.5 kΩ; CLKn pull down resistor = 50 kΩ. 5 Pin Configuration and Functions HFG Package 36-Pin CFP Top View Pin Functions(1) PIN TYPE DESCRIPTION NAME NO. CLK_SEL 2 Input Clock select. Used to select between CLK0 and CLK1 input pairs. LVTTL/LVCMOS functionality compatible. CLK0, CLK0 3, 4 Input Differential LVECL/LVPECL input pair. CLK1, CLK1 6, 7 Input Q[9:0] 12, 14, 16, 20, 22, 24, 26, 30, 32, 34 Output LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn. Q[9:0] 11, 13, 15, 19, 21, 23, 25, 29, 31, 33 Output LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn. VBB 5 Power Reference voltage output for single-ended input operation. VCC 1, 9, 10, 17, 18, 27, 28, 35, 36 Power Supply voltage. VEE 8 Power Device ground or negative supply voltage in ECL mode. |
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