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LM1881M Scheda tecnica(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte LM1881M
Spiegazioni elettronici  LM1881 Video Sync Separator
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Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM1881M Scheda tecnica(HTML) 3 Page - National Semiconductor (TI)

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Electrical Characteristics LM1881–X
V
CC = 5V; RSET = 680 k
Ω;T
A = –40˚C to +85˚C by correlation with 100% electrical testing at TA=25˚C
Parameter
Conditions
Min
Typ
Max
Units
Supply Current
Outputs at
Logic 1
V
CC =5V
V
CC = 12V
5.2
5.5
10
12
mA
DC Input Voltage
Pin 2
1.3
1.5
1.8
V
Input Threshold Voltage
55
70
85
mV
Input Discharge Current
Pin 2; V
IN = 2V
6
11
16
µA
Input Clamp Charge Current
Pin 2; V
IN = 1V
0.2
0.8
mA
R
SET Pin Reference Voltage
Pin 6;
1.10
1.22
1.35
V
Composite Sync. & Vertical
Outputs
I
OUT =40µA;
Logic 1
V
CC =5V
V
CC = 12V
4.0
11.0
4.5
V
I
OUT = 1.6 mA
Logic 1
V
CC =5V
V
CC = 12V
2.4
10.0
3.6
V
Burst Gate & Odd/Even
Outputs
I
OUT =40µA;
Logic 1
V
CC =5V
V
CC = 12V
4.0
11.0
4.5
V
Composite Sync. Output
I
OUT = −1.6 mA; Logic 0; Pin 1
0.2
0.8
V
Vertical Sync. Output
I
OUT = −1.6 mA; Logic 0; Pin 3
0.2
0.8
V
Burst Gate Output
I
OUT = −1.6 mA; Logic 0; Pin 5
0.2
0.8
V
Odd/Even Output
I
OUT = −1.6 mA; Logic 0; Pin 7
0.2
0.8
V
Vertical Sync Width
140
230
588
µs
Burst Gate Width
2.7 k
Ω from Pin 5 to V
CC
2.2
4
4.7
µs
Vertical Default Time
32
65
90
µs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For guaranteed specifications and test conditions, see the
Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
Note 2: For operation in ambient temperatures above 25˚C, the device must be derated based on a 150˚C maximum junction temperature and a package thermal
resistance of 110˚C/W, junction to ambient.
Note 3: ESD susceptibility test uses the “human body model, 100 pF discharged through a 1.5 k
Ω resistor”.
Note 4: Typicals are at TJ = 25˚C and represent the most likely parametric norm.
Note 5: Relative difference between the input clamp voltage and the minimum input voltage which produces a horizontal output pulse.
Note 6: Careful attention should be made to prevent parasitic capacitance coupling from any output pin (Pins 1, 3, 5 and 7) to the RSET pin (Pin 6).
Note 7: Delay time between the start of vertical sync (at input) and the vertical output pulse.
Typical Performance Characteristics
R
SET Value Selection
vs Vertical Serration
Pulse Separation
Vertical Default
Sync Delay Time
vs R
SET
00915007
00915008
www.national.com
3


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