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MC100EP016 Scheda tecnica(PDF) 3 Page - ON Semiconductor |
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MC100EP016 Scheda tecnica(HTML) 3 Page - ON Semiconductor |
3 / 12 page MC10EP016, MC100EP016 http://onsemi.com 3 Figure 2. 8-BIT Binary Counter Logic Diagram Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. P1 SLAVE MASTER 5 TC Q1 Q0 P7 Q6 Q5 Q4 Q3 Q2 Q1 CE Q0 BIT 1 CE Q0 Q0M Q0M PE TCLD CE P0 MR CLK BIT 7 BITS 2–6 Q7 CLK COUT COUT BIT 0 VBB VEE ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k W Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 100 V > 2 kV Moisture Sensitivity (Note 1) Level 2 Flammability Rating Oxygen Index: 28 to 34 UL 94 V–0 @ 0.125 in Transistor Count 897 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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