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M9330A Scheda tecnica(PDF) 8 Page - Keysight Technologies |
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M9330A Scheda tecnica(HTML) 8 Page - Keysight Technologies |
8 / 12 page 08 Keysight M9330A Arbitrary Waveform Generator KEY CHARACTERISTICS CONTINUED 1. A sync clock cycle is clock/8. Scenario jump modes Scenario jumps determine how a sequence responds to a jump trigger. There are no discontinuities in a scenario jump other than those imposed by the waveform data. Three modes are available to control scenario jumps: Jump immediate – Jumps immediately to the next specifie scenario address with a fixed latency. End of waveform – The current waveform (including repeats) is completed before jumping to a new scenario. End of scenario – The current scenario is completed before jumping to a new scenario. Jump latency is the longer of either the jump immediate latency or the length of the remaining scenario. Dynamic Sequencing (Option 300) Input 20-pin mini-D connector Input levels All pins configured as 2.5 volt LVCMOS inputs. A logic low must fall within the –0.2 to +0.5 volt window. A logic high must be within the window of +2.0 to +2.8 volts. Number of address bits 13 bits per channel Total number of addressable Scenarios 16 k Data rate for dynamic data 100 ns Data latency Same as front panel trigger inputs. Software pointers may also be used to point to pre-defined scenarios over the PCI backplane though latencies are not deterministic. Direct Digital Synthesis (Option 330) Output frequency resolution 1 Hz Frequency modulation Deviation from 0 to 125 MHz (250 MHz peak-peak) Phase modulation Deviation from –180 to +180 degrees in 0.022 degree steps Amplitude modulation Modulation depth from 0 to 100% with 15-bit resolution Single channel bandwidth 400 MHz (800 MHz I/Q) External triggers Number of inputs 8 each (4 SMB female frontpanel connectors plus four software triggers over the PCI backplane from host processor) Trigger polarity Negative/positive Trigger impedance 2k Ω Maximum input level ±4.5 volts Input sensitivity 250 mV Trigger threshold –4.3 volts to +4.3 volts Trigger timing resolution Clock/8 (6.4 ns at full rate) Trigger latency 34* clock/8 (217.6 ns at full rate) Trigger uncertainty < 50 ps Minimum trigger width 12.8 ns at full clock rate Trigger delay Programmable from 1 to 256 sync clock cycles with 1 sync clock cycle resolution 1 |
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