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MC100EP51DG Scheda tecnica(PDF) 2 Page - ON Semiconductor

Il numero della parte MC100EP51DG
Spiegazioni elettronici  ECL D Flip-Flop with Reset and Differential Clock
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Produttore elettronici  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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MC100EP51DG Scheda tecnica(HTML) 2 Page - ON Semiconductor

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MC10EP51, MC100EP51
http://onsemi.com
2
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
1
2
3
45
6
7
8
Q
VEE
VCC
D
Q
CLK
CLK
RESET
D
R
Flip-Flop
Table 1. PIN DESCRIPTION
PIN
CLK*, CLK*
Reset*
ECL Asynchronous Reset
FUNCTION
ECL Clock Inputs
D*
ECL Data Input
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
Table 2. TRUTH TABLE
D
L
H
X
R
L
L
H
CLK
Z
Z
X
Q
L
H
L
Z = LOW to HIGH Transition
* Pins will default LOW when left open.
EP
(DFN8 only) Thermal exposed
pad must be connected to a suf-
ficient thermal conduit. Electric-
ally connect to the most negative
supply (GND) or leave uncon-
nected, floating open.
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
TSSOP−8
DFN8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
165 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.


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