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MC10H105PG Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC10H105PG Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 5 page © Semiconductor Components Industries, LLC, 2006 August, 2016 − Rev. 8 1 Publication Order Number: MC10H105/D MC10H105 Triple 2‐3‐2‐Input OR/NOR Gate Description The MC10H105 is a triple 2-3-2-input OR/NOR gate. This MECL 10H ™ part is a functional/pinout duplication of the standard MECL 10K ™ family part, with 100% improvement in propagation delay, and no increases in power-supply current. Features • Propagation Delay, 1.0 ns Typical • Power Dissipation 25 mW/Gate (same as MECL 10K) • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K Compatible • These Devices are Pb-Free, Halogen Free and are RoHS Compliant Figure 1. Logic Diagram Figure 2. Pin Assignment VCC1 Aout Aout Ain Ain Bout Bout VEE VCC2 Cout Cout Cin Cin Bin Bin Bin 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC1 = Pin 1 VCC2 = Pin 16 VEE = Pin 8 12 15 13 14 5 2 43 11 7 9 6 10 Pin assignment is for Dual-in-Line Package. MARKING DIAGRAMS* www.onsemi.com *For additional marking information, refer to Application Note AND8002/D. A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb-Free Package PDIP−16 P SUFFIX CASE 648−08 16 1 16 1 MC10H105P AWLYYWWG PLLC−20 FN SUFFIX CASE 775−02 20 1 10H105G AWLYYWW 120 PDIP−16 PLLC−20 ORDERING INFORMATION Device Package Shipping MC10H105FNG PLLC−20 (Pb-Free) 46 Units / Tube MC10H105PG PDIP−16 (Pb-Free) 25 Units / Tube |
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