MC10E1652FNG datasheet(1/9 Pages) ONSEMI

Il numero della parte	MC10E1652FNG

Spiegazioni elettronici	Dual ECL Output Comparator with Latch

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April, 2013 − Rev. 10

1

Publication Order Number:

MC10E1652/D

MC10E1652

5V, -5V Dual ECL Output

Comparator with Latch

The MC10E1652 is fabricated using ON Semiconductor’s advanced

MOSAIC III process and is output compatible with 10H logic devices.

In addition, the device is available in a 20-pin surface mount package.

However, the MC10E1652 provides user programmable hysteresis.

The latch enable (LENa and LENb) input pins operate from standard

ECL 10H logic levels. When the latch enable is at a logic high level,

the MC10E1652 acts as a comparator; hence, Q will be at a logic high

level if V1 > V2 (V1 is more positive than V2). Q is the complement

of Q. When the latch enable input goes to a low logic level, the outputs

are latched in their present state, providing the latch enable setup and

hold time constraints are met. The level of input hysteresis is

controlled by applying a bias voltage to the HYS pin.

Features

• Typical 3.0 dB Bandwidth > 1.0 GHz

• Typical V to Q Propagation Delay of 775 ps

• Typical Output Rise/Fall of 350 ps

• Common Mode Range −2.0 V to +3.0 V

• Individual Latch Enables

• Differential Outputs

• Operating Mode: VCC = 5.0 V, VEE = −5.2 V, GND = 0 V

• Programmable Input Hysteresis

• No Internal Input Pulldown Resistors

• ESD Protection: Human Body Model; > 2 kV,

Machine Model; > 100 V

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level 3

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−O @ 0.125 in,

Oxygen Index: 28 to 34

• Transistor Count = 85 devices

• These are Pb−Free Devices*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

http://onsemi.com

MARKING

DIAGRAM

PLCC−20

FN SUFFIX

CASE 775

20 1

MC10E

1652FNG

AWLYYWW

120

A

= Assembly Location

WL

= Wafer Lot

YY

= Year

WW

= Work Week

G

= Pb−Free Package

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

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