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MC10E1651FNR2G Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC10E1651FNR2G Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 9 page © Semiconductor Components Industries, LLC, 2013 April, 2013 − Rev. 10 1 Publication Order Number: MC10E1651/D MC10E1651 5V, -5V Dual ECL Output Comparator with Latch The MC10E1651 is fabricated using ON Semiconductor’s advanced MOSAIC III process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10 KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in a 20-pin surface mount package. The latch enable (LENa and LENb) input pins operate from standard ECL 10 KH logic levels. When the latch enable is at a logic high level, the MC10E1651 acts as a comparator; hence, Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met. Features • Typical 3.0 dB Bandwidth > 1.0 GHz • Typical V to Q Propagation Delay of 775 ps • Typical Output Rise/Fall of 350 ps • Common Mode Range −2.0 V to +3.0 V • Individual Latch Enables • Differential Outputs • 28 mV Input Hysteresis • Operating Mode: VCC = 5.0 V, VEE = −5.2 V, GND = 0 V • No Internal Input Pulldown Resistors • ESD Protection: > 2 kV Human Body Model, > 100 V Machine Model • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level 3 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 • Transistor Count = 85 devices • These are Pb−Free Devices* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MARKING DIAGRAM PLCC−20 FN SUFFIX CASE 775 http://onsemi.com 20 1 MC10E 1651FNG AWLYYWW 120 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ORDERING INFORMATION |
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