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ADM1024ARUZ-REEL Scheda tecnica(PDF) 3 Page - ON Semiconductor |
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ADM1024ARUZ-REEL Scheda tecnica(HTML) 3 Page - ON Semiconductor |
3 / 30 page ADM1024 www.onsemi.com 3 Table 3. PIN ASSIGNMENT Pin No. Mnemonic Description 1 NTEST_OUT/ADD Digital I/O. Dual function pin. This is a three-state input that controls the two LSBs of the Serial Bus Address. This pin functions as an output when doing a NAND test. 2 THERM Digital I/O. Dual function pin. This pin functions as an interrupt output for temperature interrupts only, or as an interrupt input for fan control. It has an on-chip 100 k W pullup resistor. 3 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. 4 SCL Digital Input. Serial bus clock. 5 FAN1/AIN1 Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to VCC) amplitude fan tachometer input. 6 FAN2/AIN2 Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to VCC) amplitude fan tachometer input. 7 CI Digital I/O. An active high input from an external latch that captures a Chassis Intrusion event. This line can go high without any clamping action, regardless of the powered state of the ADM1024. The ADM1024 provides an internal open drain on this line, controlled by Bit 6 of Register 40h or Bit 7 of Register 46h, to provide a minimum 20 ms pulse on this line to reset the external Chassis Intrusion Latch. 8 GND System Ground. 9 VCC Power (2.8 V to 5.5 V). Typically powered from 3.3 V power rail. Bypass with the parallel combination of 10 mF (electrolytic or tantalum) and 0.1 mF (ceramic) bypass capacitors. 10 INT Digital Output. Interrupt request (open-drain). The output is enabled when Bit 1 of Register 40h is set to 1. The default state is disabled. It has an on-chip 100 k W pullup resistor. 11 NTEST_IN/AOUT Digital Input/Analog Output. An active-high input that enables NAND Test mode board-level connectivity testing. Refer to the section on NAND testing. Also functions as a programmable analog output when NAND Test is not selected. 12 RESET Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 45 ms minimum pulse width. Set using Bit 4 in Register 40h. Also acts as reset input when pulled low (e.g., power-on reset). It has an on-chip 100 k W pullup resistor. 13 D1− Analog Input. Connected to cathode of first external temperature-sensing diode. 14 D1+ Analog Input. Connected to anode of first external temperature-sensing diode. 15 +12 VIN Programmable Analog Input. Monitors 12 V supply. 16 +5.0 VIN Analog Input. Monitors 5.0 V supply. 17 VCCP2/D2– Programmable Analog Input. Monitors second processor core voltage or cathode of second external temperature-sensing diode. 18 +2.5 VIN/D2+ Programmable Analog Input. Monitors 2.5 V supply or anode of second external temperature-sensing diode. 19 +VCCP1 Analog Input. Monitors first processor core voltage (0 V to 3.6 V). 20 VID4/IRQ4 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID4 Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k W pullup resistor. 21 VID3/IRQ3 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k W pullup resistor. 22 VID2/IRQ2 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k W pullup resistor. 23 VID1/IRQ1 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k W pullup resistor. 24 VID0/IRQ0 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 k W pullup resistor. |
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