GS81313LT18/36GK-833/714/625

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.13 7/2016

11/29

© 2014, GSI Technology

NOPr and NOPw Requirements

The number of NOPw and NOPr needed during Write -> Read transitions, and the number of NOPr and NOPw needed during Read

-> Write transitions, are as follows:

Write -> Read Transition

Read -> Write Transition

NOPw (after Write)

NOPr (before Read)

NOPr (after Read)

NOPw (before Write)

min

typ

min

typ

min

typ

min

typ

0

0

0

1~2

2

3~4

3

4~5

Notes:

1. Min NOPw after Write (0) ensures that the SRAM disables DQ ODT 2.5 cycles after it latches the last piece of write data. Typ

NOPw is the same as Min NOPw because it is sufficient to ensure that the controller stops driving the last piece of write data

before SRAM DQ ODT disable reaches it (as the result of a subsequent NOPr or Read), regardless of SRAM tKQ, prop delay

between SRAM and controller, and operating frequency.

2. Min NOPr before Read (0) ensures that the SRAM drives Low 1 cycle before it begins driving the first piece of read data. Typ

NOPr is greater than Min NOPr in order to ensure that the controller enables DQ ODT after SRAM Low drive reaches it (and

before the SRAM drives the first piece of read data), accounting for SRAM tKQ, prop delay between SRAM and controller, and

operating frequency.

3. Min NOPr after Read (2) ensures that the SRAM drives Low for 1 cycle after it stops driving the last piece of read data and before

it enables DQ ODT (as the result of a subsequent NOPw). Typ NOPr is greater than Min NOPr in order to ensure that the controller

disables DQ ODT after SRAM Low drive reaches is (and before the SRAM enables DQ ODT), accounting for SRAM tKQ, prop

delay between SRAM and controller, and operating frequency.

4. Min NOPw before Write (3) ensures that the SRAM enables DQ ODT 1 cycle before it latches the first piece of write data. Typ

NOPw is greater than Min NOPw in order to ensure that the controller begins driving the first piece of write data after SRAM

DQ ODT enable reaches it, accounting for SRAM tKQ, prop delay between SRAM and controller, and operating frequency.

DQ ODT Control Timing Diagram

A3

A1

A2

CK, KD

SA

LD

DQ

CQ

Read1

NOPr2

NOPr3

NOPr4

NOPw1

R/W

NOPw2

NOPw3

NOPw4

Q21

Write1

NOPr1

D11 D12

Q22

D31

Write2

Note: In the diagram above, the controller is disabling its DQ ODT except from the beginning of NOPr4 to the beginning of NOPw3.

And while it is disabling its DQ ODT, the controller is driving DQ Low when it isn’t driving write data. Whereas, the SRAM is

enabling its DQ ODT except from the beginning of NOPr2 to the beginning of NOPw3. And while it is disabling its DQ ODT, the

SRAM is driving DQ Low when it isn’t driving read data.