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GS81313LT18 Scheda tecnica(PDF) 4 Page - GSI Technology |
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GS81313LT18 Scheda tecnica(HTML) 4 Page - GSI Technology |
4 / 29 page GS81313LT18/36GK-833/714/625 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.13 7/2016 4/29 © 2014, GSI Technology Pin Description Symbol Description Type SA Address — Read or Write Address is registered on CK. Input DQ[35:0] Write/Read Data — Registered on KD and KD during Write operations; aligned with CQ and CQ during Read operations. DQ[17:0] - x18 and x36. DQ[35:18] - x36 only. I/O QVLD[1:0] Read Data Valid — Driven high one half cycle before valid Read Data. Output CK, CK Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing control, and for output timing control. Input KD[1:0], KD[1:0] Write Data Input Clocks — Dual single-ended. Used for latching write data inputs. KD0, KD0: latch Write Data (DQ[17:0] in x36, DQ[8:0] in x18). KD1, KD1: latch Write Data (DQ[35:18] in x36, DQ[17:9] in x18). Input CQ[1:0], CQ[1:0] Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs. Facilitate source-synchronous operation. CQ0, CQ0: align with DQ[17:0] in x36, and DQ[8:0] in x18. CQ1, CQ1: align with DQ[35:18] in x36, and DQ[17:9] in x18. Output LD Load Enable — Registered on CK. LD = 0: Loads a new address and initiates a Read or Write operation. LD = 1: Initiates a NOP operation. Input R/W Read / Write Enable — Registered on CK. R/W = 0: initiates a Write operation when LD = 0. R/W = 1: initiates a Read operation when LD = 0. Input PLL PLL Enable — Weakly pulled High internally. PLL = 0: disables internal PLL. PLL = 1: enables internal PLL. Input RST Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High. Weakly pulled Low internally. Input ZQ Driver Impedance Control Resistor Input — Must be connected to VSS through an external resistor RQ to program driver impedance. Input ZT ODT Impedance Control Resistor Input — Must be connected to VSS through an external resistor RT to program ODT impedance. Input RCS Current Source Resistor Input — Must be connected to VSS through an external 2K resistor to provide an accurate current source for the PLL. Input MZT[1:0] ODT Mode Select — Set the ODT state globally for all input groups. Must be tied High or Low. MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0]. MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0]. MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0]. MZT[1:0] = 11: reserved. Input |
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