Pin Description Table

Symbol

Description

Type

Comments

SA

Synchronous Address Inputs

Input

—

R/W

Read/Write Contol Pin

Input

Write Active Low; Read Active High

NW0–NW1

Synchronous Nybble Writes

Input

Active Low

x08 Only

BW

Synchronous Byte Writes

Input

Active Low

x09 Only

BW0–BW3

Synchronous Byte Writes

Input

Active Low

x18/x36 Only

K

Input Clock

Input

Active High

C

Output Clock

Input

Active High

TMS

Test Mode Select

Input

—

TDI

Test Data Input

Input

—

TCK

Test Clock Input

Input

—

TDO

Test Data Output

Output

—

HSTL Input Reference Voltage

Input

—

ZQ

Output Impedance Matching Input

Input

—

K

Input Clock

Input

Active Low

C

Output Clock

Output

Active Low

DLL Disable

—

Active Low

LD

Synchronous Load Pin

—

Active Low

CQ

Output Echo Clock

Output

Active Low

CQ

Output Echo Clock

Output

Active High

Dn

Synchronous Data Inputs

Input

—

Qn

Synchronous Data Outputs

Output

—

Power Supply

Supply

1.8 V Nominal

Isolated Output Buffer Supply

Supply

1.8 or 1.5 V Nominal

Power Supply: Ground

Supply

—

NC

No Connect

—

—

Notes:

unconnected.

3. NC = Not Connected to die or any other pin.

GS8182S08/09/18/36BD-400/375/333/300/250/200/167

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.03c 11/2011

6/36

© 2007, GSI Technology

Background

Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the

other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are

needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a

separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control