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GS81313LD18 Scheda tecnica(PDF) 8 Page - GSI Technology |
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GS81313LD18 Scheda tecnica(HTML) 8 Page - GSI Technology |
8 / 26 page GS81313LD18/36GK-833/714/625 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.13 7/2016 8/26 © 2014, GSI Technology Clock Truth Table Previous Operation SA R W Current Operation D Q (tn–1) CK (tn) CK (tn) CK (tn) (tn) KD (tn-1) KD (tn-½) KD (tn) KD (tn+½) CQ (tn+3) CQ (tn+3½) CQ (tn+4) CQ (tn+4½) NOP X 1 1 NOP X X — — 0 — Write X 1 X NOP D3 D4 — — 0 — Read X X 1 NOP X X — — Q3 Q4 — NOP V 1 0 Write D1 D2 D3 D4 0 — Read V X 0 Write D1 D2 D3 D4 Q3 Q4 — NOP V 0 X Read X X — — Q1 Q2 Q3 Q4 Write V 0 X Read D3 D4 — — Q1 Q2 Q3 Q4 Notes: 1. 1 = High; 0 = Low; V = Valid; X = don’t care. 2. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of Write Data transferred during Write operations. 3. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of Read Data transferred during Read operations. 4. Q pins are driven Low for one cycle in response to NOP and Write commands, 3 cycles after the command is sampled, except when pre- ceded by a Read command. |
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