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FM24CL04-S Scheda tecnica(PDF) 2 Page - List of Unclassifed Manufacturers |
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FM24CL04-S Scheda tecnica(HTML) 2 Page - List of Unclassifed Manufacturers |
2 / 12 page FM24CL04 Rev. 2.0 July 2003 Page 2 of 12 Address Latch ` 128 x 32 FRAM Array Data Latch 8 SDA Counter Serial to Parallel Converter Control Logic SCL WP A1 A2 Figure 1. Block Diagram Pin Description Pin Name I/O Pin Description A1-A2 Input Address 1-2: The address pins set the device select address. The device address value in the 2-wire slave address must match the setting of these two pins. These pins are internally pulled down. SDA I/O Serial Data/Address: This is a bi-directional pin used to shift serial data and addresses for the two-wire interface. It employs an open-drain output and is intended to be wire- OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. A pull-up resistor is required. SCL Input Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL input also incorporates a Schmitt trigger input for improved noise immunity. WP Input Write Protect: When WP is high the entire array is write protected. When WP is low, all addresses may be written. This pin is internally pulled down. NC - No connect VDD Supply Supply Voltage VSS Supply Ground |
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