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FDS7779Z Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor |
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FDS7779Z Scheda tecnica(HTML) 4 Page - Fairchild Semiconductor |
4 / 5 page FDS7779Z Rev C1 (W) 0 2 4 6 8 10 0 10 2030 405060 7080 Qg, GATE CHARGE (nC) ID = -16A VDS = -10V -15V -20V 0 1000 2000 3000 4000 5000 0 5 10 15 20 25 30 -VDS, DRAIN TO SOURCE VOLTAGE (V) CISS COSS CRSS f = 1 MHz VGS = 0 V 0.01 0.1 1 10 100 0.01 0.1 1 10 100 -VDS, DRAIN-SOURCE VOLTAGE (V) DC 1s 100ms 100 µs RDS(ON) LIMIT VGS = -10V SINGLE PULSE RθJA = 125 oC/W TA = 25 oC 10ms 1ms 10s 0 10 20 30 40 50 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) SINGLE PULSE RθJA = 125°C/W TA = 25°C 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) RθJA(t) = r(t) * RθJA RθJA = 125 oC/W TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 P(pk) t1 t2 SINGLE PULSE 0.01 0.02 0.05 0.1 0.2 D = 0.5 Typical Characteristics Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design. |
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