ESS Technology, Inc.

SAM0368-030601

3

ES1988 PRODUCT BRIEF

PIN DESCRIPTION

Table 1 lists the ES1988 pin descriptions

.

Table 1

ES1988 Pin Descriptions

Names

Pin Numbers

I/O

Descriptions

C/BE[3:0]#

1, 13, 20, 30

I/O

PCI command/byte enable. During address phase of a transaction, these pins define the bus

command. During data phase, these pins define the byte enable.

IDSEL

2

I

ID select. When pin 2 is configured as a multifunction pin (see pin 2 note), IDSEL is selected

internally to AD24.

R0#

I

PCI bus request 0 input from external PCI master device. RO# is enabled by setting the PCIx2

arbiter bit PCI 58h [0] = 1. Select RO# from pin 2 by setting PCI 58h [10] = 1, and pin 2 must be

configured as a multifunction pin. Either pin 2 or pin 52 may be used for R0#.

SPDIFO

O

S/PDIF output. Enable SPDIFO by setting PCI 53h [0] = 1. Select SPDIFO from pin 2 by setting

PCI 58h [1] = 1, and pin 2 must be configured as a multifunction pin. Either pin 2 or pin 54 may

be used for SPDIFO.

PCREQ#

O

PC/PCI request output. Enable PCREQ# by setting PCI 50h [10:8] = 010. Pin 53 is used as

PCREQ# when configured as an audio-only device. PCREQ# can only be used from pin 2 when

the ES1988 is configured as a multifunction device (see pin 60 note). Pin 2 must be configured

as a multifunction pin.

GND

3, 21, 40, 89

I

Digital ground.

AD[31:0]

4:11, 22:29,

31:38, 93:100

I/O

Address and data lines from the PCI bus.

VCC

12, 41, 90

I

Digital supply voltage, 3.3V.

FRAME#

14

I/O

Cycle frame.

IRDY#

15

I/O

Initiator ready.

TRDY#

16

I/O

Target ready.

DEVSEL#

17

I/O

Device select.

STOP#

18

I/O

Stop transaction.

PAR

19

I/O

Parity.

CLKRUN#

39

I/O

Input/output for PCI Clock status and an output to start or accelerate clock function by enabling

PCI 52h [11] = 1.

ECS

O

Chip select output to EEPROM chip select input. ECS is active after power-on reset and goes

inactive automatically after EEPROM cycle is complete.

GD[0]

42

I/O

Game port data input/output.

GD[1]

43

I/O

Game port data input/output.

EDOUT

O

Data output to EEPROM data input. EDOUT goes active after power-on reset and goes inactive

automatically after EEPROM cycle is complete.

GD[2]

44

I/O

Game port data input/output.

EDIN

I

Data input from EEPROM data output. EDIN goes active after power-on reset and goes inactive

automatically after EEPROM cycle is complete.

VOLUP#

I

Hardware volume control (volume up). Used in combination with pin 45 (VOLDN#). Hardware

volume control is enabled by setting PCI 52 [7] = 1. Pins 44:45 are selected for hardware volume

control by setting PCI 52h [5] = 1. Pins 53:54 may also be used for hardware volume control.