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MC10H100L Scheda tecnica(PDF) 1 Page - ON Semiconductor |
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MC10H100L Scheda tecnica(HTML) 1 Page - ON Semiconductor |
1 / 4 page © Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 6 1 Publication Order Number: MC10H100/D MC10H100 Quad 2-Input NOR Gate With Strobe The MC10H100 is a quad NOR gate. Each gate has 3 inputs, two of which are independent and one of which is tied common to all four gates. • Propagation Delay, 1.0 ns Typical • 25 mW Typ/Gate (No Load) • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K–Compatible DIP PIN ASSIGNMENT VCC1 AOUT BOUT AIN AIN BIN BIN VEE VCC2 DOUT COUT DIN DIN CIN CIN COMMON INPUT (A, B, C, D) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 LOGIC DIAGRAM VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 4 5 9 2 3 14 15 2 = 4 + 5 + 9 6 7 10 11 12 13 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). http://onsemi.com Device Package Shipping ORDERING INFORMATION MC10H100L CDIP–16 25 Units/Rail MC10H100P PDIP–16 25 Units/Rail MC10H100FN PLCC–20 46 Units/Rail MARKING DIAGRAMS 1 16 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week CDIP–16 L SUFFIX CASE 620 MC10H100L AWLYYWW PDIP–16 P SUFFIX CASE 648 PLCC–20 FN SUFFIX CASE 775 10H100 AWLYYWW 1 1 16 MC10H100P AWLYYWW |
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