STK11C68-M

4-36

Note n:

The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a

STORE cycle or (0000, 1555, 0AAA,1FFF, 10F0, 0F0E)

for a

RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details.

Note o: I/O state assumes that G

STORE CYCLE INHIBIT and AUTOMATIC POWER-UP RECALL

MODE SELECTION

NONVOLATILE MEMORY OPERATION

H

X

X

Not Selected

Output High Z

Standby

L

H

X

Read SRAM

Output Data

Active

o

L

L

X

Write SRAM

Input Data

Active

L

H

0000

Read SRAM

Output Data

Active

n,o

1555

Read SRAM

Output Data

n,o

0AAA

Read SRAM

Output Data

n,o

1FFF

Read SRAM

Output Data

n,o

10F0

Read SRAM

Output Data

n,o

0F0F

Nonvolatile

STORE

Output High Z

n

L

H

0000

Read SRAM

Output Data

Active

n,o

1555

Read SRAM

Output Data

n,o

0AAA

Read SRAM

Output Data

n,o

1FFF

Read SRAM

Output Data

n,o

10F0

Read SRAM

Output Data

n,o

0F0E

Nonvolatile

RECALL

Output High Z

n

EW

A

MODE

I/O

POWER

NOTES

2

4.0

5.0V

t

STORE inhibit

Automatic

RECALL