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STK11C68-5K45M Scheda tecnica(PDF) 2 Page - List of Unclassifed Manufacturers

Il numero della parte STK11C68-5K45M
Spiegazioni elettronici  CMOS NV SRAM
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Produttore elettronici  ETC [List of Unclassifed Manufacturers]
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STK11C68-5K45M Scheda tecnica(HTML) 2 Page - List of Unclassifed Manufacturers

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STK11C68-M
4-32
ICC
b
Average VCC Current
90
mA
tAVAV = 35ns
85
mA
t
AVAV = 45ns
80
mA
tAVAV = 55ns
ICC
d
Average VCC Current
50
mA
E
≥ (V
CC – 0.2V)
during STORE cycle
all others V
IN ≤ 0.2V or ≥ (VCC – 0.2V)
ISB
c
Average VCC Current
27
mA
tAVAV = 35ns
(Standby, Cycling TTL Input Levels)
23
mA
tAVAV = 45ns
20
mA
t
AVAV = 55ns
E
≥ V
IH; all others cycling
ISB
c
Average VCC Current
2
mA
E
≥ (V
CC – 0.2V)
(Standby, Stable CMOS Input Levels)
all others V
IN ≤ 0.2V or ≥ (VCC – 0.2V)
IILK
Input Leakage Current (Any Input)
±1
µAV
CC = max
VIN = VSS to VCC
I
OLK
Off State Output Leakage Current
±5
µAV
CC = max
VIN = VSS to VCC
VIH
Input Logic "1" Voltage
2.2
VCC+.5
V
All Inputs
VIL
Input Logic "0" Voltage
VSS–.5
0.8
V
All Inputs
VOH
Output Logic "1" Voltage
2.4
V
IOUT = –4mA
V
OL
Output Logic "0" Voltage
0.4
V
I
OUT = 8mA
TA
Operating Temperature
–55
125
°C
ABSOLUTE MAXIMUM RATINGSa
Voltage on typical input relative to VSS. . . . . . . . . . . . . –0.6V to 7.0V
Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V)
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55
°C to 125°C
Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65
°C to 150°C
Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W
DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
Note a: Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions above
those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
(One output at a time, one second duration)
DC CHARACTERISTICS
(VCC = 5.0V ± 10%)
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS to 3V
Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . .
≤ 5ns
Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
CAPACITANCEe (T
A=25°C, f=1.0MHz)
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
5.0V
Output
480 Ohms
30pF
INCLUDING
SCOPE
AND FIXTURE
255 Ohms
CIN
Input Capacitance
5
pF
∆V = 0 to 3V
C
OUT
Output Capacitance
7
pF
∆V = 0 to 3V
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
1
2
1
2
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
Note b: ICC is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: Bringing E
≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note d: ICC is the average current required for the duration of the store cycle (tSTORE) after the sequence (tWC) that initiates the cycle.
2
1


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