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TPD3S014DBVR Scheda tecnica(PDF) 5 Page - Texas Instruments |
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TPD3S014DBVR Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 29 page TPD3S014, TPD3S044 www.ti.com SLVSCP4B – OCTOBER 2014 – REVISED AUGUST 2015 7.4 Thermal Information TPD3S0x4 THERMAL METRIC(1)(2) DBV (SOT-23) UNIT 6 PINS RθJA Junction-to-ambient thermal resistance 185.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 124.7 °C/W RθJB Junction-to-board thermal resistance 32.0 °C/W ψJT Junction-to-top characterization parameter 23.7 °C/W ψJB Junction-to-board characterization parameter 31.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA(Custom) See the Power Dissipation and Junction Temperature section 120.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) See Device Comparison Table. 7.5 Electrical Characteristics: TJ = TA = 25°C Unless otherwise noted: VIN = 5 V, VEN = VIN, IOUT = 0 A. See Device Comparison Table for the rated current of each part number. Parametrics over a wider operational range are shown in the second Electrical Characteristics: –40°C ≤ TJ ≤ 125°C table. PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT POWER SWITCH TPD3S014 97 110 TPD3S014: –40°C ≤ (TJ, TA) ≤ 85°C 96 130 RDS(on) Input – Output resistance m Ω TPD3S044 74 91 TPD3S044: –40°C ≤ (TJ, TA) ≤ 85°C 74 106 CURRENT LIMIT TPD3S014 0.67 0.85 1.01 IOS (2) Current limit, see Figure 27 A TPD3S044 1.70 2.15 2.50 SUPPLY CURRENT IOUT = 0A 0.02 1 ISD Supply current, switch disabled µA –40°C ≤ (TJ, TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A 2 IOUT = 0A 66 74 ISE Supply current, switch enabled µA –40°C ≤ (TJ, TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A 85 VOUT = 5 V, VIN = 0 V, Measure IVOUT 0.2 1 IREV Reverse leakage current µA –40°C ≤ (TJ, TA) ≤ 85°C, VOUT = 5 V, VIN = 0 V, 5 measure IVOUT OUTPUT DISCHARGE RPD Output pull-down resistance(3) VIN = VOUT = 5 V, disabled 400 456 600 Ω ESD PROTECTION Differential capacitance between ΔCIO ƒ = 1 MHz, VIO = 2.5 V 0.02 pF the D1, D2 lines CIO (D1, D2 to GND) ƒ = 1 MHz, VIO = 2.5 V 1.4 pF Dx to GND Dynamic on-resistance D1, D2 RDYN 0.2 Ω IEC clamps(4) GND to Dx (1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature (2) See Current Limit for explanation of this parameter. (3) These Parameters are provided for reference only, and do not constitute a part of TI’s published device specifications for purposes of TI’s product warranty. (4) RDYN was extracted using the least squares first of the TLP characteristics between I = 20 A and I = 30 A. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPD3S014 TPD3S044 |
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