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UC3825NG4 Scheda tecnica(PDF) 5 Page - Texas Instruments |
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UC3825NG4 Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 19 page 5 UC1825 UC2825 UC3825 High speed circuits demand careful attention to layout and component placement. To assure proper perfor- mance of the UC1825 follow these rules: 1) Use a ground plane. 2) Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the out- put pins to ring below ground. A series gate resistor or a shunt 1 Amp Schottky diode at the output pin will serve this purpose. 3) Bypass VCC,VC, and VREF. Use 0.1 µF monolithic ceramic capacitors with low equivalent series inductance. Allow less than 1 cm of total lead length for each capacitor between the bypassed pin and the ground plane. 4) Treat the timing capacitor, CT, like a bypass ca- pacitor. Open Loop Frequency Response Unity Gain Slew Rate Simplified Schematic Error Amplifier Circuit PWM Applications Conventional (Voltage Mode) Current-Mode Printed Circuit Board Layout Considerations |
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