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TL16C2552IFNR Scheda tecnica(PDF) 1 Page - Texas Instruments |
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TL16C2552IFNR Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 34 page www.ti.com FEATURES APPLICATIONS DESCRIPTION TL16C2552 SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS • False-Start Bit Detection • Programmable Auto-RTS and Auto-CTS • Complete Status Reporting Capabilities • In Auto-CTS Mode, CTS Controls the • 3-State Output TTL Drive Capabilities for Transmitter Bidirectional Data Bus and Control Bus • In Auto-RTS Mode, RCV FIFO Contents, and • Line Break Generation and Detection Threshold Control RTS • Internal Diagnostic Capabilities: • Serial and Modem Control Outputs Drive a – Loopback Controls for Communications RJ11 Cable Directly When Equipment is on Link Fault Isolation the Same Power Drop – Break, Parity, Overrun, and Framing Error • Capable of Running With All Existing Simulation TL16C450 Software • Fully Prioritized Interrupt System Controls • After Reset, All Registers Are Identical to the • Modem Control Functions (CTS, RTS, DSR, TL16C450 Register Set DTR, RI, and DCD) • Up to 24-MHz Clock Rate for up to 1.5-Mbaud • Available in 44-Pin PLCC (FN) or 32-Pin QFN Operation With VCC = 5 V (RHB) Packages • Up to 20-MHz Clock Rate for up to • Each UART's Internal Register Set May Be 1.25-Mbaud Operation With VCC = 3.3 V Written Concurrently to Save Setup Time • Up to 16-MHz Clock Rate for up to 1-Mbaud • Multi-Function Output (MF) Allows Users to Operation With VCC = 2.5 V Select Among Several Functions, Saving • Up to 10-MHz Clock Rate for up to 625-kbaud Package Pins Operation With VCC = 1.8 V • In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise • Point-of-Sale Terminals Synchronization Between the CPU and Serial • Gaming Terminals Data • Portable Applications • Programmable Baud Rate Generator Allows • Router Control Division of Any Input Reference Clock by 1 to • Cellular Data (216 - 1) and Generates an Internal 16 × Clock • Factory Automation • Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream The TL16C2552 is a dual universal asynchronous • 5-V, 3.3-V, 2.5-V, and 1.8 V Operation receiver and transmitter (UART). It incorporates the • Independent Receiver Clock Input functionality of two TL16C550D UARTs, each UART having its own register set and FIFOs. The two • Transmit, Receive, Line Status, and Data Set UARTs share only the data bus interface and clock Interrupts Independently Controlled source, otherwise they operate independently. • Fully Programmable Serial Interface Another name for the UART function is Characteristics: Asynchronous Communications Element (ACE), and – 5-, 6-, 7-, or 8-Bit Characters these terms will be used interchangeably. The bulk of this document describes the behavior of each – Even-, Odd-, or No-Parity Bit Generation ACE, with the understanding that two such devices and Detection are incorporated into the TL16C2552. – 1-, 1 ½-, or 2-Stop Bit Generation – Baud Generation (dc to 1 Mbit/s) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2005–2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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