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TL16C2552 Scheda tecnica(PDF) 2 Page - Texas Instruments

Il numero della parte TL16C2552
Spiegazioni elettronici  1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

TL16C2552 Scheda tecnica(HTML) 2 Page - Texas Instruments

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RXA
MFA
D5
D6
RIB
DSRB
CDB
TXRDYB
VCC
INTA
RTSA
DTRA
TXA
39
35
31
29
30
32
33
34
36
37
38
2
4
6
1
42
40
41
43
44
3
5
7
8
9
10
11
12
13
14
15
16
17
19
18
26
28
20 21 22 23 24 25
27
A0
XTAL1
GND
XTAL2
A1
A2
CHSEL
INTB
D7
TL16C2552FN
FN PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
D6
D7
A0
XTAL1
XTAL2
A1
A2
CHSEL
RXA
TXA
RTSA
INTA
GND
NC
NC
CTSB
RHB PACKAGE
(TOP VIEW)
NC − No internal connection
NOTE: The 32-pin RHB package does not provide access to DSRA,
DSRB, RIA, RIB, CDA, CDB inputs and MFA, MFB, DTRA, DTRB,
TXRDYA, TXRDYB outputs.
TL16C2552RHB
TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
Each ACE is a speed and voltage range upgrade of
the TL16C550C, which in turn is a functional
upgrade of the TL16C450. Functionally equivalent to
the TL16C450 on power up or reset (single character
or TL16C450 mode), each ACE can be placed in an
alternate FIFO mode. This relieves the CPU of
excessive software overhead by buffering received
and to be transmitted characters. Each receiver and
transmitter store up to 16 bytes in their respective
FIFOs,
with
the
receive
FIFO
including
three
additional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can
significantly reduce software overload and increase
system efficiency by automatically controlling serial
data flow using handshakes between the RTS output
and CTS input, thus eliminating overruns in the
receive FIFO.
Each ACE performs serial-to-parallel conversions on
data received from a peripheral device or modem
and stores the parallel data in its receive buffer or
FIFO, and each ACE performs parallel-to-serial
conversions on data sent from its CPU after storing
the parallel data in its transmit buffer or FIFO. The
CPU can read the status of either ACE at any time.
Each
ACE
includes
complete
modem
control
capability and a processor interrupt system that can
be tailored to the application.
Each ACE includes a programmable baud rate
generator capable of dividing a reference clock with
divisors of from 1 to 65535, thus producing a 16×
internal reference clock for the transmitter and
receiver logic. Each ACE accommodates up to a
1.5-Mbaud serial data rate (24-MHz input clock). As
a reference point, that speed would generate a
667-ns bit time and a 6.7-µs character time (for 8,N,1
serial data), with the internal clock running at 24
MHz.
Each ACE has a TXRDY and RXRDY output that
can be used to interface to a DMA controller.
2
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