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TL16PNP550A Scheda tecnica(PDF) 7 Page - Texas Instruments |
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TL16PNP550A Scheda tecnica(HTML) 7 Page - Texas Instruments |
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7 / 40 page  TL16PNP550A ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH PLUGANDPLAY (PnP) AND AUTOFLOW CONTROL SLLS190B − MARCH 1995 − REVISED MARCH 1996 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions (Continued) TERMINAL NAME NO. FN I/O DESCRIPTION RI 61 I Ring indicator. RI is modem status signal. Its condition can be checked by reading bit 6 (RI) of the MSR. BIt 2 (TERI) of the MSR indicates that RI has transitioned from a low to a high level since the last read from the MSR. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated. RTS 49 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS is set to its active level low by setting the RTS modem control register bit and is set to its inactive (high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR. In auto-RTS mode, RTS is set to its inactive level by the receiver threshold control logic. SCLK 55 O 3-state EEPROM clock. SCLK is a 3-state EEPROM clock output that controls address and data transfer. A 100 µA pulldown circuit is connected to this terminal. SIN 6 I Serial data. SIN is input from a connected communications device. SIO 57 I/O 3-State bidirectional EEPROM serial data bus. During output mode, SIO provides only read opcode and address which are sourced at the falling edge of SCLK. During input mode it provides the data which is captured at the rising edge of SCLK. A 100 µA pulldown circuit is connected to this terminal. SOUT 51 O Composite serial data output to a connected communication device. SOUT is set to the marking (high) level as a result of master reset. UARTBYPASS 7 I UART bypass. When it is active, UARTBYPASS disables the UART and the TL16PNP550A acts as a PnP stand-alone controller. VCC 5, 22, 39, 56 5-V supply voltage. XIN, XOUT 63, 64 I/O External clock. XIN and XOUT connect the TL16PNP550A to the main timing reference, a 22-MHz clock or crystal. detailed description autoflow control Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the input must be active before the transmitter FIFO can emit data (see Figure 1). Auto-RTS becomes active when the receiver needs more data and notifies the sending serial device (see Figure 1). When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated if ACE1 and ACE2 are TL16PNP550As with enabled autoflow control. If autoflow control is not enabled, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency. RCV FIFO Serial to Parallel Flow Control XMT FIFO Parallel to Serial Flow Control Parallel to Serial Flow Control Serial to Parallel Flow Control XMT FIFO RCV FIFO ACE1 ACE2 D7 − D0 SIN SOUT RTS CTS SOUT SIN CTS RTS D7 − D0 Figure 1. Autoflow Control Example (Auto-RTS and Auto-CTS) |
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