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93AA46AE48TI Scheda tecnica(PDF) 7 Page - Microchip Technology |
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93AA46AE48TI Scheda tecnica(HTML) 7 Page - Microchip Technology |
7 / 26 page 2013-2016 Microchip Technology Inc. DS20005229C-page 7 93AA46AE48 2.5 Erase All (ERAL) The Erase All (ERAL) instruction will erase the entire memory array to the logical ‘1’ state. The ERAL cycle is identical to the erase cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). VCC must be ≥4.5V for proper operation of ERAL. FIGURE 2-2: ERAL TIMING Note: After the ERAL command is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. CS CLK DI DO TCSL Check Status 10 0 1 0 x ••• x TSV TCZ Busy Ready High Z TEC High-Z Note: VCC must be ≥4.5V for proper operation of ERAL. |
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