Write-Control

Logic

RAM ARRAY

512 × 18, 1024 ×18,

2048 × 18, 4096 ×18

Offset

Register

Input

Register

Flag

Logic

Read

Pointer

Read-Control

Logic

Output

Register

Write

Pointer

Expansion

Logic

Reset

Logic

(HF)/WXO

WXI

FL

RXI

RXO

RS

WEN

WCLK

D0–D17

LD

HF/(WXO)

PAE

EF/OR

PAF

FF/IR

Q0–Q17

OE

REN

RCLK

19

20

18

21

26

24

27

57

59

58

61

60

25

23

54

17

26

SN74V245-EP

SCAS932A – DECEMBER 2012 – REVISED JANUARY 2013

www.ti.com

The SN74V245 is depth expandable, using a daisy-chain technique or FWFT mode. The XI and XO pins are

used to expand the FIFOs. In depth-expansion configuration, first load (FL) is grounded on the first device and

set to high for all other devices in the daisy chain.

The SN74V245 is characterized for operation from –55°C to 125°C.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE

ORDERABLE PART NUMBER

TOP-SIDE MARKING

VID NUMBER

–55°C to 125°C

64-pin TQFP (PAG)

SN74V245-15PAGEP

V245-15EP

V62/13606-01XE

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

FUNCTIONAL BLOCK DIAGRAM

2

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Product Folder Links: SN74V245-EP