SN74LVC1G125

SCES223T – APRIL 1999 – REVISED OCTOBER 2014

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9 Detailed Description

9.1 Overview

The SN74LVC1G125 device contains one buffer gate device with output enable control and performs the

circuitry disables the outputs, preventing damaging current backflow through the device when it is powered

down.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves

significant board space over other package options while still retaining the traditional manufacturing friendly lead

pitch of 0.5 mm.

9.2 Functional Block Diagram

9.3 Feature Description

•

Wide operating voltage range

–

Operates from 1.65 V to 5.5 V

•

Allows down voltage translation

•

Inputs accept voltages to 5.5 V

•

9.4 Device Functional Modes

Table 1. Function Table

INPUTS

OUTPUT

Y

OE

A

L

H

H

L

L

L

H

X

Z

10

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